82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet - Page 15

• Manufacturer Part Number: 82V2044BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-7 AIS Condition
Table-5 Configuration of the Line Code Rule
Table-6 LOS Condition in Clock Recovery Mode
1.
to ‘0’ or pulling pin CODE low. AMI rule is enabled by setting bit CODE in
register GCF to ‘1’ or pulling pin CODE high. The settings affect all four
channels.
setting bit SINGn in register e-SING to ‘1’ (to activate bit CODEn in
register e-CODE) and programming bit CODEn to select line code rules
in the corresponding channel: ‘0’ for B8ZS/HDB3, while ‘1’ for AMI. In
this case, the value in bit CODE in register GCF or pin CODE for global
control is unaffected in the corresponding channel and only affect in
other channels.
register GCF, bit CODEn in register e-CODE and pin CODE are ignored.
2.4.5
recovery, as shown in Table-7.
AIS Detected
Detected
LOS levels at device (RTIPn, RRINGn) with all ones signal. For more detail regarding the LOS parameters, please refer to
AIS Cleared
IDT82V2044
Cleared
Functional Description
Line code rule selection for each channel, if needed, is available by
In dual rail mode, the decoder/encoder are bypassed. Bit CODE in
The configuration of the line code rule is summarized in Table-5.
Alarm Indication Signal is available only in host mode with clock
CODE
LOS
LOS
High
Low
ALARM INDICATION SIGNAL (AIS) DETECTION
Continuous Intervals
All channels in B8ZS/HDB3
All channels in AMI
Less than 3 zeros contained in each of two
consecutive 512-bit stream are received
3 or more zeros contained in each of two
consecutive 512-bit stream are received
Amplitude
Amplitude
Hardware Mode
Density
(Register LAC defaulted to ‘0’)
Line Code Rule
(1)
(1)
ITU G.775 for E1
below typical 200 mVp
12.5% (16 marks in a sliding 128-bit
period) with no more than 99 contin-
uous zeros
exceed typical 250 mVp
ANSI T1.231 for T1
175
Less than 3 zeros contained in a 512-bit
stream are received
3 or more zeros contained in a 512-bit
stream are received
CODE in GCF
(Register LAC set to ‘1’)
ETSI 300 233 for E1
0
0
1
1
0
1
below typical 200 mVp
12.5% (4 marks in a sliding 32-bit
period) with no more than 15 con-
tinuous zeros
exceed typical 250 mVp
15
2.4.4
the received signal on receiver line before the transformer (measured on
port A, B shown in Figure-12). The loss condition is reported by pulling
pin LOSn high. At the same time, LOS alarm registers track LOS condi-
tion. When LOS is detected or cleared, an interrupt will generate if not
masked. In host mode, the detection supports the ANSI T1.231 for T1
mode, ITU G.775 and ETSI 300 233 for E1 mode. In hardware mode, it
supports the ITU G.775 and ANSI T1.231.
register GCF is set to ‘0’ or output all ones as AIS (alarm indication
signal) when bit AISE is set to ‘1’. The RCLKn is replaced by MCLK only
if the bit AISE is set.
CODEn in e-CODE
The Loss of Signal Detector monitors the amplitude and density of
Table-6
During LOS, the RDPn/RDNn output the sliced data when bit AISE in
G.775 for E1
Standard
32
LOSS OF SIGNAL (LOS) DETECTION
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
0/1
0/1
0
1
1
0
summarizes the conditions of LOS in clock recovery mode.
Less than 9 zeros contained in a 8192-bit stream (a ones
density of 99.9% over a period of 5.3 ms) are received
9 or more zeros contained in a 8192-bit stream are
received
Host Mode
Receiver Characteristics on page
SINGn in e-SING
below typical 200 mVp
12.5% (4 marks in a sliding 32-bit
period) with no more than 15 con-
tinuous zeros
exceed typical 250 mVp
0
1
0
1
1
1
ETSI 300 233 for E1
ANSI T1.231 for T1
2048 (1 ms)
All channels in B8ZS/HDB3
All channels in AMI
CHn in AMI
CHn in B8ZS/HDB3
September 22, 2005
48.
Line Code Rule
Signal on
LOSn
High
Low