82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet - Page 5

• Manufacturer Part Number: 82V2044BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-1 Pin Description (Continued)
IDT82V2044
Pin Description
RD0/RDP0
RD1/RDP1
RD2/RDP2
RD3/RDP3
CV0/RDN0
CV1/RDN1
CV2/RDN2
CV3/RDN3
TCLK0
TCLK1
TCLK2
TCLK3
Name
High-Z
Type
O
I
TQFP144
36
29
81
74
40
33
77
70
41
34
76
69
Pin No.
PBGA160
N14
M13
M12
L14
P13
P12
M2
M3
N1
P2
P3
L1
TCLKn: Transmit Clock for Channel 0~3
The clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) for transmit is input on this pin. The
transmit data at TDn/TDPn or TDNn is sampled into the device on the falling edges of TCLKn.
Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in Transmit All
Ones (TAOS) state (when MCLK is clocked). In TAOS state, the TAOS generator adopts MCLK as the
clock reference.
If TCLKn is low, the corresponding transmit channel is set into power down state, while driver output ports
become high-Z.
Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as the fol-
lows:
RDn: Receive Data for Channel 0~3
In Single Rail mode, the received NRZ data is output on this pin. The data is decoded by AMI or B8ZS/
HDB3 line code rule.
CVn: Code Violation for Channel 0~3
In Single Rail mode, the bipolar violation, code violation and excessive zeros will be reported by driving pin
CVn high for a full clock cycle. However, only bipolar violation is indicated when AMI decoder is selected.
RDPn/RDNn: Positive/Negative Receive Data for Channel 0~3
In Dual Rail Mode with clock recovery, these pins output the NRZ data. A high signal on RDPn indicates
the receipt of a positive pulse on RTIPn/RRINGn while a high signal on RDNn indicates the receipt of a
negative pulse on RTIPn/RRINGn.
The output data at RDn or RDPn/RDNn are clocked out on the falling edges of RCLK when the CLKE input
is low, or are clocked out on the rising edges of RCLK when CLKE is high.
In Dual Rail Mode without clock recovery, these pins output the raw RZ sliced data. In this data recovery
mode, the active polarity of RDPn/RDNn is determined by pin CLKE. When pin CLKE is low, RDPn/RDNn
is active low. When pin CLKE is high, RDPn/RDNn is active high.
In hardware mode, RDn or RDPn/RDNn will remain active during LOS. In host mode, these pins will either
remain active or insert alarm indication signal (AIS) into the receive path, determined by bit AISE in regis-
ter GCF.
RDn or RDPn/RDNn is set into high-Z when the corresponding receiver is powered down.
High/Low
High/Low
Clocked
Clocked
Clocked
MCLK
TCLK1 is unavail-
able.
High (≥ 16 MCLK)
Low (≥ 64 MCLK) The corresponding transmit channel is set into power down state.
TCLK1 is clocked
Clocked
TCLKn
5
Normal operation
Transmit All Ones (TAOS) signals to the line side in the corresponding
transmit channel.
TCLKn is clocked Normal operation
TCLKn is high
(≥ 16 TCLK1)
TCLKn is low
(≥ 64 TCLK1)
The receive path is not affected by the status of TCLK1. When MCLK
is high, all receive paths just slice the incoming data stream. When
MCLK is low, all the receive paths are powered down.
All four transmitters (TTIPn & TRINGn) will be in high-Z.
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
Description
Transmit All Ones (TAOS) signals to the line side
in the corresponding transmit channel.
Corresponding transmit channel is set into power
down state.
Transmit Mode
September 22, 2005