82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet - Page 25

• Manufacturer Part Number: 82V2044BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-14 Parallel Host Interface Pins
2.18 INTERFACE WITH 5 V LOGIC
The internal input pads are tolerant to 5 V output from TTL and CMOS
family devices.
2.19 HOST INTERFACE
the device. The interface consists of serial host interface and parallel
host interface. By pulling pin MODE2 to VDDIO/2 or high, the device can
be set to work in serial mode and in parallel mode respectively.
2.19.2 SERIAL HOST INTERFACE
host Mode. In this mode, the registers are accessible through a 16-bit
word which contains an 8-bit command/address byte (bit R/W and 5-
address-bit A1~A5, A6 and A7 bits are ignored) and a subsequent 8-bit
data byte (D7~D0), as shown in Figure-21. When bit R/W is set to ‘1’,
data is read out from pin SDO. When bit R/W is set to ‘0’, data on pin
SDI is written into the register whose address is indicated by address
bits A5~A1.
IDT82V2044
Functional Description
The IDT82V2044 can interface directly with 5 V TTL family devices.
The host interface provides access to read and write the registers in
By pulling pin MODE2 to VDDIO/2, the device operates in the serial
MODE[2:0]
101
110
111
100
SDO
CS
SCLK
SDI
1. While R/W=1, read from IDT82V2044; While R/W=0, write to IDT82V2044.
2. Ignored.
R/W
Figure-21 Serial Host Mode Timing
1
A1
Address/Command Byte
Non-multiplexed Motorola interface
High Impedance
A2
Non-multiplexed Intel interface
Multiplexed Motorola interface
Multiplexed Intel interface
A3
A4 A5 A6
Host Interface
25
2
A7
2.19.1 PARALLEL HOST INTERFACE
MODE1 and MODE0 are used to select the operating mode of the
parallel host interface. When pin MODE1 is pulled low, the host uses
separate address bus and data bus. When high, multiplexed address/
data bus is used. When pin MODE0 is pulled low, the parallel host inter-
face is configured for Motorola compatible hosts. When pin MODE0 is
pulled high, the parallel host interface is configured for Intel compatible
hosts. See
pins in each operation mode is tabulated in Table-14:
2
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
The interface is compatible with Motorola and Intel host. Pins
Driven while R/W=1
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
Input Data Byte
Table-1 Pin Description
CS, RDY, WR, RD, ALE, A[4:0], D[7:0], INT
CS, ACK, DS, R/W, AS, A[4:0], D[7:0], INT
Generic Control, Data and Output Pin
CS, RDY, WR, RD, ALE, AD[7:0], INT
CS, ACK, DS, R/W, AS, AD[7:0], INT
for more details. The host interface
September 22, 2005