A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 64

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SmartFusion DC and Switching Characteristics
Figure 2-20 • Input DDR Timing Diagram
Table 2-74 • Input DDR Propagation Delays
2- 52
Out_QR
Out_QF
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDRICLKQ1
DDRICLKQ2
DDRISUD
DDRIHD
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
Data
CLK
CLR
For derating values at specific junction temperature and voltage-supply levels, refer to
for derating values.
Worst Commercial-Case Conditions: T
Timing Characteristics
t
t
1
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR
Data Hold for Input DDR
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal time for Input DDR
Asynchronous Clear Recovery time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
DDRICLR2Q2
DDRICLR2Q1
t
DDRIREMCLR
2
3
t
DDRICLKQ1
Description
4
J
= 85°C, Worst Case VCC = 1.425 V
2
R e visio n 6
3
5
t
DDRICLKQ2
t
DDRISUD
6
4
5
7
t
DDRIHD
Table 2-7 on page 2-9
t
8
DDRIRECCLR
6
7
0.39
0.29
0.00
0.23
0.22
0.36
0.32
0.28
0.00
0.58
0.47
350
–1
9
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns