A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 61

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-17 • Output Register Timing Diagram
Table 2-71 • Output Data Register Propagation Delays
Enable
Preset
Clear
DOUT
CLK
Data_out
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OCLKQ
OSUD
OHD
OSUE
OHE
OCLR2Q
OPRE2Q
OREMCLR
ORECCLR
OREMPRE
ORECPRE
OWCLR
OWPRE
OCKMPWH
OCKMPWL
For the derating values at specific junction temperature and voltage supply levels, refer to
page 2-9
Worst Commercial-Case Conditions: T
Output Register
Timing Characteristics
Clock-to-Q of the Output Data Register
Data Setup Time for the Output Data Register
Data Hold Time for the Output Data Register
Enable Setup Time for the Output Data Register
Enable Hold Time for the Output Data Register
Asynchronous Clear-to-Q of the Output Data Register
Asynchronous Preset-to-Q of the Output Data Register
Asynchronous Clear Removal Time for the Output Data Register
Asynchronous Clear Recovery Time for the Output Data Register
Asynchronous Preset Removal Time for the Output Data Register
Asynchronous Preset Recovery Time for the Output Data Register
Asynchronous Clear Minimum Pulse Width for the Output Data Register
Asynchronous Preset Minimum Pulse Width for the Output Data Register
Clock Minimum Pulse Width High for the Output Data Register
Clock Minimum Pulse Width Low for the Output Data Register
for derating values.
50%
50%
t
1
OSUE
t
OHE
50%
50%
t
OSUD
0
t
t
OHD
OCLKQ
50%
50%
Description
50%
t
OWPRE
t
OPRE2Q
J
50%
50%
= 85°C, Worst-Case VCC = 1.425 V
R e v i s i o n 6
t
t
ORECPRE
50%
OCLR2Q
50%
t
OWCLR
50%
50%
50%
SmartFusion Intelligent Mixed Signal FPGAs
t
ORECCLR
50%
t
OCKMPWH
t
50%
OREMPRE
0.60
0.32
0.00
0.44
0.00
0.82
0.82
0.00
0.23
0.00
0.23
0.22
0.22
0.36
0.32
–1
t
50%
OCKMPWL
0.72
0.38
0.00
0.53
0.00
0.98
0.98
0.00
0.27
0.00
0.27
0.22
0.22
0.36
0.32
Std.
Table 2-7 on
t
OREMCLR
50%
50%
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 49