A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 39

FPGA - Field Programmable Gate Array 500K System Gates

A2F500M3G-FGG256

Manufacturer Part Number
A2F500M3G-FGG256
Description
FPGA - Field Programmable Gate Array 500K System Gates
Manufacturer
Actel
Datasheet

Specifications of A2F500M3G-FGG256

Processor Series
A2F500
Core
ARM Cortex M3
Number Of Logic Blocks
24
Maximum Operating Frequency
100 MHz
Number Of Programmable I/os
117
Data Ram Size
64 KB
Delay Time
50 ns
Supply Voltage (max)
3.6 V
Supply Current
2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
500000
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A2F500M3G-FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A2F500M3G-FGG256
Manufacturer:
ALTERA
0
Company:
Part Number:
A2F500M3G-FGG256
Quantity:
1 060
Part Number:
A2F500M3G-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A2F500M3G-FGG256I
Manufacturer:
MICROSEMI/美高森美
Quantity:
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Table 2-27 • I/O Output Buffer Maximum Resistances
Table 2-28 • I/O Weak Pull-Up/Pull-Down Resistances
Standard
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance
2. R
3. R
VCCxxxxIOBx
3.3 V
2.5 V
1.8 V
1.5 V
Notes:
1. R
2. R
values depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located on the
SoC Products Group website at http://www.actel.com/download/ibis/default.aspx.
(PULL-DOWN-MAX)
(PULL-UP-MAX)
(WEAK PULL-DOWN-MAX)
(WEAK PULL-UP-MAX)
Applicable to MSS I/O Banks
Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
= (V
= (V
CCImax
= (V
OLspec
= (V
CCImax
Min.
10 k
11 k
18 k
19 k
– V
OLspec
) / I
R
OHspec
(WEAK PULL-UP)
OLspec
– V
) / I
OHspec
) / I
(Ω)
(WEAK PULL-DOWN-MIN)
OHspe c
R e v i s i o n 6
) / I
(WEAK PULL-UP-MIN)
Drive Strength
1
Max.
45 k
55 k
70 k
90 k
8 mA
4 mA
2 mA
8mA
1
SmartFusion Intelligent Mixed Signal FPGAs
Min.
10 k
12 k
17 k
19 k
R
R
PULL-DOWN
(WEAK PULL-DOWN)
(Ω)
100
200
50
50
2
(Ω)
R
110 k
140 k
Max.
45 k
74 k
PULL-UP
2
(Ω)
150
100
224
112
3
2- 27

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