A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 37

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-23 • Summary of I/O Timing Characteristics—Software Default Settings
Table 2-24 • Summary of I/O Timing Characteristics—Software Default Settings
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI
3.3 V PCI-X
LVDS
LVPECL
Notes:
1. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See
2. For specific junction temperature and voltage supply levels, refer to
I/O Standard
3.3 V LVTTL /
3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
Notes:
1. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See
2. For specific junction temperature and voltage supply levels, refer to
connectivity. This resistor is not required during normal operation.
connectivity. This resistor is not required during normal operation.
–1 Speed Grade, Worst Commercial-Case Conditions: T
Worst-Case VCCxxxxIOBx (per standard)
Applicable to FPGA I/O Banks, Assigned to EMC I/O Pins
–1 Speed Grade, Worst Commercial-Case Conditions: T
Worst-Case VCCxxxxIOBx (per standard)
Applicable to MSS I/O Banks
Per PCI spec High
Per PCI-X
8 mA
8 mA
4 mA
2 mA
12 mA
12 mA
12 mA
12 mA
24 mA
24 mA
spec
High
High
High
High
High
High
High
High
High
High
High
10
10
10
10
35
35
35
35
10
10
–
–
–
–
–
–
25
25
–
–
–
–
–
–
0.18 1.92 0.07 0.78 1.09 0.18 1.96 1.55 1.83 2.04
0.18 1.96 0.07 0.99 1.16 0.18 2.00 1.82 1.82 1.93
0.18 2.31 0.07 0.91 1.37 0.18 2.35 2.27 1.84 1.87
0.18 2.70 0.07 1.07 1.55 0.18 2.75 2.67 1.87 1.85
1
1
0.50 2.81 0.03 0.81 0.32 2.86 2.23 2.55 2.82 4.58 3.94 ns
0.50 2.73 0.03 1.03 0.32 2.88 2.69 2.62 2.70 4.60 4.41 ns
0.50 2.81 0.03 0.95 0.32 2.87 2.38 2.92 3.18 4.58 4.10 ns
0.50 3.24 0.03 1.12 0.32 3.30 2.79 3.10 3.27 5.02 4.50 ns
0.50 2.11 0.03 0.68 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns
0.50 2.11 0.03 0.64 0.32 2.15 1.57 2.55 2.82 3.87 3.28 ns
0.50 1.53 0.03 1.55
0.50 1.46 0.03 1.46
R e v i s i o n 6
Table 2-7 on page 2-9
Table 2-7 on page 2-9
J
J
SmartFusion Intelligent Mixed Signal FPGAs
= 85°C, Worst Case VCC = 1.425 V,
= 85°C, Worst Case VCC = 1.425 V,
–
–
–
–
–
–
for derating values.
for derating values.
Figure 2-10 on page 2-39
Figure 2-10 on page 2-39
–
–
–
–
–
–
–
–
ns
ns
ns
ns
2- 25
ns
ns
for
for