A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 104

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SmartFusion Development Tools
SmartFusion Ecosystem
3 - 2
The MSS configurator includes the following:
The SoC Products Group has a long history of supplying comprehensive FPGA development tools and
recognizes the benefit of partnering with industry leaders to deliver the optimum usability and productivity
to users. Taking the same approach to processor development, The SoC Products Group has partnered
with key industry leaders in the microcontroller space to provide a robust solution that can be easily
adopted by existing embedded developers and has an easy learning path for FPGA designers. The SoC
Products Group is partnering with Keil and IAR to provide software IDE support to SmartFusion
Designers. In addition, Micrium provides support for SmartFusion with its new µC/OS-III,™ TCP/IP,™
and µC/Probe™ products
Support for the SoC Products Group device and ecosystem resources is represented in
Figure 3-2 • SmartFusion Ecosystem
Starting from the base up, the ARM
hardware abstraction layer (HAL) is built on top of the SmartFusion hardware platform. Each of the
peripherals has its own driver, whether it is hard IP or soft IP added in the FPGA fabric. Then on top of
that we will work with third party real-time operating system (RTOS) vendors for OS, protocol stacks, and
interfaces. A designer can add a custom application with all, some, or none of the layers below.
Application Code
•
•
•
•
•
Physical Layer
Middleware
A simple configurator for the embedded designer to control the MSS peripherals and I/Os
A method to import and view a hardware configuration from the FPGA flow into the embedded
flow containing the memory map
Automatic generation of drivers for any peripherals or soft IP used in the system configuration
Comprehensive analog configuration for the programmable analog components
Creation of a standard MSS block to be used in SmartDesign for connection of FPGA fabric
designs and IP
Drivers
RTOS
HAL
(Table 3-1 on page
RTOS – Real-Time Operating System
Protocol Stacks, File Systems,
Hardware Abstraction Layer
Target Hardware Platform
®
Application Layer
Cortex™ Microcontroller Software Interface Standard (CMSIS)
Interfaces
R e vi s i o n 6
3-3).
Customer Alogorithms/
Intellectual Property
Third Party
TCP, HTTP, SMTP
DHCP, LCD
Third Party µC/OSII
Actel or Third Party
For Hard IP or Soft IP
I
RAM, 10/100, Timer
Actel CMSIS-based
Actel SmartFusion
2
C, SPI, UART, NVM
Figure
3-2.