A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 183

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6 – Datasheet Information
List of Changes
Revision
Revision 6
(March 2011)
The following table lists critical changes that were made in each revision of the SmartFusion datasheet.
The
A2F200 and A2F500 (SAR 31005).
The
for A2F060 and the PQ208 package for A2F200 and A2F500. A row was added for
shared analog inputs (SAR 31034).
The
VCCESRAM was added to
Recommended Operating
Characteristics, and the
The following note was removed from
Characteristics
"Current monitors and temperature monitors should not be used when Power-Down
and/or Sleep mode are required by the application."
Dynamic power values were updated in the following tables. The table subtitles
changed where FPGA I/O banks were involved to note "I/O assigned to EMC I/O pins"
(SAR 30987).
Table 2-9 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software
Settings
Table 2-12 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software
Settings.
The
Values in the timing tables for the following sections were updated. Table subtitles
were updated for FPGA I/O banks to note "I/O assigned to EMC I/O pins " (SAR
30986).
"Overview of I/O Performance"
"Detailed I/O DC Characteristics"
Table
Table
"LVDS"
"LVPECL"
"Global Tree Timing Characteristics"
The
Global clocks were removed from the A2F060 pin table for the
"256-Pin FBGA"
31033).
"SmartFusion Device Status" table
"Timing Model"
"208-Pin PQFP"
"PQ208"
"Package I/Os: MSS + FPGA I/Os" table
2-43,
2-56,
section:
section:
Table
Table
package was added to product tables and
(SAR 30984):
Table 2-64
packages, resulting in changed function names for affected pins (SAR
2-57,
2-44,
Table 2-67
was updated (SAR 30986).
section and pin tables are new (SAR 31005).
Table
"Supply Pins" table
Table
Conditions,
2-60,
Table 2-1 • Absolute Maximum
2-45,
section:
Table 2-61
section:
Table
Changes
R e v i s i o n 6
section:
was updated (SAR 31084
Table
Table 2-8 • Quiescent Supply Current
2-49,
(SAR 31035).
Table 2-8 • Quiescent Supply Current
Table
2-23,
was revised to add the CS288 package
Table
Table
2-79,
Table 2-24
2-37,
2-50,
"Product Ordering Codes"
Table 2-80
Table
Table
Ratings,
)
.
"288-Pin CSP"
2-38,
2-51,
Table 2-3 •
Table
Table
2-39,
2-55,
and
for
2-10,
2-1, 2-3,
Page
2-10
2-10
2-19
2-23
2-26
2-40
2-43
2-60
5-33
5-41
2-11
III
III
III
5-1
6 -1