A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 38

FPGA - Field Programmable Gate Array 500K System Gates

A2F500M3G-FGG256

Manufacturer Part Number
A2F500M3G-FGG256
Description
FPGA - Field Programmable Gate Array 500K System Gates
Manufacturer
Actel
Datasheet

Specifications of A2F500M3G-FGG256

Processor Series
A2F500
Core
ARM Cortex M3
Number Of Logic Blocks
24
Maximum Operating Frequency
100 MHz
Number Of Programmable I/os
117
Data Ram Size
64 KB
Delay Time
50 ns
Supply Voltage (max)
3.6 V
Supply Current
2 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
500000
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A2F500M3G-FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A2F500M3G-FGG256
Manufacturer:
ALTERA
0
Company:
Part Number:
A2F500M3G-FGG256
Quantity:
1 060
Part Number:
A2F500M3G-FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A2F500M3G-FGG256I
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
SmartFusion DC and Switching Characteristics
2- 26
Detailed I/O DC Characteristics
Table 2-25 • Input Capacitance
Table 2-26 • I/O Output Buffer Maximum Resistances
Symbol
C
C
Standard
3.3 V LVTTL / 3.3 V LVCMOS
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS
3.3 V PCI/PCI-X
Notes:
1. These maximum values are provided for information only. Minimum output buffer resistance values
2. R
3. R
IN
INCLK
depend on VCCxxxxIOBx, drive strength selection, temperature, and process. For board design
considerations and detailed output buffer resistances, use the corresponding IBIS models located on the
Microsemi SoC Products Group website at
generated by the SoC Products Group Libero IDE toolset).
(PULL-DOWN-MAX)
(PULL-UP-MAX)
Input capacitance
Input capacitance on the clock pin
Applicable to FPGA I/O Banks
= (V
= (V
CCImax
OLspec
Definition
– V
) / I
OHspec
OLspec
) / I
Per PCI/PCI-X specification
OHspe c
R e visio n 6
Drive Strength
http://www.actel.com/download/ibis/default.aspx
12 mA
16 mA
24 mA
12 mA
16 mA
24 mA
12 mA
16 mA
12 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
6 mA
8 mA
1
V
V
IN
IN
= 0, f = 1.0 MHz
= 0, f = 1.0 MHz
Conditions
R
PULL-DOWN
(Ω)
100
100
100
100
200
100
200
100
50
50
25
17
11
50
50
25
20
11
50
50
20
20
67
33
33
25
Min.
2
Max.
8
8
R
PULL-UP
(Ω)
300
300
150
150
200
200
100
100
225
224
112
112
75
50
33
50
40
22
56
56
22
22
75
37
37
75
Units
3
pF
pF
(also

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