A2F500M3G-FGG256 Actel, A2F500M3G-FGG256 Datasheet - Page 27

• Manufacturer Part Number: A2F500M3G-FGG256
• Description: FPGA - Field Programmable Gate Array 500K System Gates
• Manufacturer: Actel

Specifications of A2F500M3G-FGG256

• Processor Series: A2F500
• Core: ARM Cortex M3
• Number Of Logic Blocks: 24
• Maximum Operating Frequency: 100 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 64 KB
• Delay Time: 50 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 2 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.5 V
• Number Of Gates: 500000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Clock Dynamic Contribution—P
Sequential Cells Dynamic Contribution—P
Combinatorial Cells Dynamic Contribution—P
Routing Net Dynamic Contribution—P
Standby Mode
P
Time Keeping Mode
P
SoC Mode
P
Standby Mode and Time Keeping Mode
P
SoC Mode
P
Standby Mode and Time Keeping Mode
P
SoC Mode
P
Standby Mode and Time Keeping Mode
P
SoC Mode
P
DYN
DYN
CLOCK
CLOCK
S-CELL
S-CELL
C-CELL
C-CELL
NET
N
Table 2-16 on page
N
on page
F
N
N
sequential cell is used, it should be accounted for as 1.
α
F
N
α
F
N
N
α
F
CLK
CLK
CLK
CLK
SPINE
ROW
S-CELL
S-CELL
C-CELL
S-CELL
C-CELL
1
1
1
= (N
= P
= P
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
= (P
= 0 W
= N
= 0 W
= N
= 0 W
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the frequency of the clock driving the logic including these nets.
RC-OSC
LPXTAL-OSC
S-CELL
is the number of VersaTile rows used in the design—guidelines are provided in
is the number of global spines used in the user design—guidelines are provided in
S-CELL
C-CELL
is the number of VersaTiles used as combinatorial modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as sequential modules in the design. When a multi-tile
is the number VersaTiles used as sequential modules in the design.
AC1
2-18.
+ N
+ N
+ P
* (
* (P
SPINE
LPXTAL-OSC
C-CELL
α
AC5
1
2-18.
/ 2) * P
* P
+ (
) * (
AC2
α
α
AC7
1
1
/ 2) * P
+ N
/ 2) * P
* F
ROW
CLK
AC6
R e v i s i o n 6
AC8
* PAC3 + N
NET
CLOCK
) * F
* F
S-CELL
CLK
CLK
C-CELL
S-CELL
SmartFusion Intelligent Mixed Signal FPGAs
* P
AC4
) * F
CLK
Table 2-16 on page
Table 2-16 on page
Table 2-16 on page
Table 2-16
2-18.
2-18.
2-18.
2- 15