MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 93

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

The following pseudocode explains basic MAC or MSAC instruction functionality. This example is
presented as a case statement covering the three basic operating modes with signed integers, unsigned
integers, and signed fractionals. Throughout this example, a comma-separated list in curly brackets, {},
indicates a concatenation operation.
switch (MACSR[6:5])
{
Freescale Semiconductor
case 0:
•
if (MACSR.OMC == 0 || MACSR.PAVn == 0)
The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where <<1
indicates a left shift and >>1 indicates a right shift. The shift is performed before the product is
added to or subtracted from the accumulator. Without this operator, the product is not shifted. If the
EMAC is in fractional mode (MACSR[F/I] is set), SF is ignored and no shift is performed. Because
a product can overflow, the following guidelines are implemented:
— For unsigned word and longword operations, a zero is shifted into the product on right shifts.
— For signed, word operations, the sign bit is shifted into the product on right shifts unless the
— For all left shifts, a zero is inserted into the lsb position.
if ((product[63:39] != 0x0000_00_0) and and
then {
product is zero. For signed, longword operations, the sign bit is shifted into the product unless
an overflow occurs or the product is zero, in which case a zero is shifted in.
MACSR.PAVn = 0
/* select the input operands */
if (sz == word)
/* perform the multiply */
product[63:0] = operandY[31:0] * operandX[31:0]
/* check for product overflow */
then {if (U/Ly == 1)
}
else {operandY[31:0] = Ry[31:0]
}
then {
}
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
then operandY[31:0] = {sign-extended Ry[31], Ry[31:16]}
then operandX[31:0] = {sign-extended Rx[31], Rx[31:16]}
/* MACSR[S/U, F/I] */
/* signed integers */
else operandY[31:0] = {sign-extended Ry[15], Ry[15:0]}
if (U/Lx == 1)
else operandX[31:0] = {sign-extended Rx[15], Rx[15:0]}
operandX[31:0] = Rx[31:0]
MACSR.PAVn = 1
MACSR.V = 1
if (inst == MSAC and and
then if (product[63] == 1)
else if (MACSR.OMC == 1)
/* product overflow */
then result[47:0] = 0x0000_7fff_ffff
else result[47:0] = 0xffff_8000_0000
then /* overflowed MAC,
if (product[63] == 1)
then result[47:0] = 0xffff_8000_0000
else result[47:0] = 0x0000_7fff_ffff
saturationMode enabled */
MACSR.OMC == 1)
(product[63:39] != 0xffff_ff_1))
Enhanced Multiply-Accumulate Unit (EMAC)
3-15