MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 231

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MCF5282CVF80J

Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet

Specifications of MCF5282CVF80J

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Note the following characteristics of a basic read:
States are described in
13.4.4
During a write cycle, the processor sends data to the memory or to a peripheral device. The write cycle
flowchart is shown in
Freescale Semiconductor
A[31:0], SIZ[1:0]
CSn, BSn, OE
In S3, data is made available by the external device on the falling edge of CLKOUT and is sampled
on the rising edge of CLKOUT with TA asserted.
In S4, the external device can stop driving data after the rising edge of CLKOUT. However data
could be driven up to S5.
For a read cycle, the external device stops driving data between S4 and S5.
CLKOUT
D[31:0]
Write Cycle
1.
2.
3.
4.
5.
6.
1.
2.
1.
R/W
TIP
TS
TA
Set R/W to write
Place address on A[31:0]
Assert TIP and SIZ[1:0]
Assert TS
Place data on D[31:0]
Negate TS
Sample TA low
Stop driving data from D[31:0]
Start next cycle
ColdFire processor
Figure
Table
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
13-3.
13-7.
Figure 13-6. Basic Read Bus Cycle
Figure 13-7. Write Cycle Flowchart
S0
S1
S2
S3
Read
1.
2.
3.
1.
S4
Decode address
Store data on D[31:0]
Assert TA
Negate TA
External Device
S5
External Interface Module (EIM)
13-7

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