MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 738
MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Revision History
B.2
B-2
Table 6-12 on page
Table 6-13 on page
Table 6-14 on page
Figure 6-1 on page
“Register Memory
Figure 32-1 on
Table 32-1 on
Table 33-3 on
Appendix A,
6.3.4.3/6-10
6.3.4.3/6-10
6.4.3.1/6-17
6.4.3.1/6-17
6.4.3.1/6-17
6.4.3.1/6-17
6.4.3.1/6-17
6.4.3.1/6-17
page 32-2
page 32-4
page 33-3
Location
Location
6.2/6-2
Map
6-16
6-19
6-23
6-3
Changes Between Rev. 0.1 and Rev. 1
Changed “RAS0” and “RAS1” to “SDRAM_CS0” and “SDRAM_CS1.”
Added
Changed max input high voltage to 5.25 V.
Changed “System Integration Module” to “System Control Module.”
Replaced
Enhanced discussion of Flash blocks.
Added “Note:
Added “Note:
of the external reset configuration.”
Changed text in Step 1 to read “If f
Changed equation in Step 2 to the following:
Changed equation in Step 3 to the following:
Changed equations in example to reflect revisions above.
Changed text to read “So, for f
is a valid frequency for the timing of program and erase functions.”
Changed text to read “Consider the follwoing example for f
Added “Page erase verify” category.
Added “Page erase verify” category and description.
Added “Access error” row.
Table
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 6-1
Table B-1. Rev. 0 to Rev. 0.1 Changes (continued)
32-1.
Enabling Flash security will disable BDM communications.”
When Flash security is enabled, the chip will boot in single chip mode regardless
Table B-2. Rev. 0.1 to Rev. 1 Changes
with a more accurate block diagram.
f
CLK
DIV[5:0] =
SYS
=
= 66 MHz, writing 0x54 to CFMCLKD will set FCLK to 196.43 kHz which
SYS
2 x (DIV[5:0] + 1) x (1 + (PRDIV8 x 7))
÷ 2 is greater than 12.8 MHz, PRDIV8 = 1; otherwise PRDIV8 = 0.”
2 x 200kHz x (1 + (PRDIV8 x 7))
Description
Description
f
SYS
f
SYS
SYS
= 66 MHz.”
Freescale Semiconductor
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