MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 486

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

FlexCAN
To exit low-power stop mode:
When in low-power stop mode, a recessive to dominant transition on the CAN bus causes the WAKEINT
bit in the error and status register (ESTAT) to be set. This event can generate an interrupt if the WAKEMSK
bit in CANMCR is set.
Consider the following notes regarding low-power stop mode:
25-16
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Reset the FlexCAN either by asserting RSTI or by setting the SOFTRST bit CANMCR.
Clear the STOP bit in CANMCR.
The FlexCAN module can optionally exit low-power stop mode via the self-wake mechanism. If
the SELFWAKE bit in CANMCR was set at the time the FlexCAN entered stop mode, then upon
detection of a recessive to dominant transition on the CAN bus, the FlexCAN clears the STOP bit
in CANMCR and its clocks begin running.
When the self-wake mechanism activates, the FlexCAN tries to receive the frame that woke it up.
(It assumes that the dominant bit detected is a start-of-frame bit). It will not arbitrate for the CAN
bus at this time.
The CPU should disable all interrupts in the FlexCAN before entering low-power stop mode.
Otherwise it may be interrupted while in STOP mode upon a non wake-up condition; If desired,
the WAKEMASK bit should be set to enable the WAKEINT.
If the STOP bit is set while the FlexCAN is in the bus off state, then the FlexCAN will enter
low-power stop mode and stop counting recessive bit times. The count will continue when STOP
is cleared.
To place the FlexCAN in low-power stop mode with the self-wake mechanism engaged, write to
CANMCR with both STOP and SELFWAKE set, then wait for the FlexCAN to set the STOPACK
bit.
To take the FlexCAN out of low-power stop mode when the self-wake mechanism is enabled, write
to CANMCR with both STOP and SELFWAKE clear, then wait for the FlexCAN to clear the
STOPACK bit.
The SELFWAKE bit should not be set after the FlexCAN has already entered low-power stop
mode.
If both STOP and SELFWAKE are set and a recessive to dominant edge immediately occurs on the
CAN bus, the FlexCAN may never set the STOPACK bit, and the STOP bit will be cleared.
To prevent old frames from being sent when the FlexCAN awakes from low-power stop mode via
the self-wake mechanism, disable all transmit sources, including transmit buffers configured for
remote request responses, before placing the FlexCAN in low-power stop mode.
If the FlexCAN is in debug mode when the STOP bit is set, the FlexCAN will assume that debug
mode should be exited. As a result, it will try to synchronize with the CAN bus, and only then will
it await the conditions required for entry into low-power stop mode.
Unlike other modules, the FlexCAN does not come out of reset in low-power stop mode. The basic
FlexCAN initialization procedure (see
should be executed before placing the module in low-power stop mode.
If the FlexCAN is in low-power stop mode with the self-wake mechanism engaged and is operating
with a single system clock per time quantum, there can be extreme cases in which FlexCAN
wake-up on recessive to dominant edge may not conform to the CAN protocol. FlexCAN
synchronization will be shifted one time quantum from the wake-up event. This shift lasts until the
next recessive to dominant edge, which resynchronizes the FlexCAN to be in conformance with
the CAN protocol. The same holds true when the FlexCAN is in auto-power save mode and
awakens on a recessive to dominant edge.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Section 25.4.10, “FlexCAN Initialization
Freescale Semiconductor
Sequence”)