MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 244

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Signal Descriptions
14-4
SDRAM write enable
SDRAM bank selects
SDRAM clock enable
Reset in
Reset out
EXTAL
XTAL
Clock output
Clock mode
Reset configuration
External interrupts
Management data
Management data clock EMDC
Transmit clock
Transmit enable
Transmit data 0
Collision
Receive clock
Signal Name
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 14-1. MCF5282 Signal Description (continued)
DRAMW
SDRAM_CS[1:0]
SCKE
RSTI
RSTO
EXTAL
XTAL
CLKOUT
CLKMOD[1:0]
RCON
IRQ[7:1]
EMDIO
ETXCLK
ETXEN
ETXD0
ECOL
ERXCLK
Abbreviation
(not available on MCF5214 and MCF5216)
Chip Configuration Module
External Interrupt Signals
Ethernet Module Signals
Clock and Reset Signals
Asserted to signify that a DRAM write
cycle is underway. Negated to indicate
a read cycle.
Interface to the chip-select lines of the
SDRAMs within a memory block.
SDRAM clock enable.
Asserted to enter reset exception
processing.
Automatically asserted with RSTI.
Negation indicates that the PLL has
regained its lock.
Driven by an external clock except
when used as a connection to the
external crystal.
Internal oscillator connection to the
external crystal.
Reflects the system clock.
Clock mode select
Reset configuration select
External interrupt sources.
Transfers control information between
the external PHY and the media
access controller.
for data transfers on the EMDIO signal.
ETXEN, ETXD[3:0], and ETXER.
present on the MII.
Asserted to indicate a collision.
ERXDV, ERXD[3:0], and ERXER.
Provides a timing reference to the PHY
Provides a timing reference for
Indicates when valid nibbles are
Serial output Ethernet data.
Provides a timing reference for
Function
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Freescale Semiconductor
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