MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 627

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

30.4.3
The ABLR and ABHR, shown in
be used as part of the trigger. These register values are compared with the address for each transfer on the
processor’s high-speed local bus. The trigger definition register (TDR) identifies the trigger as one of three
cases:
Freescale Semiconductor
1. Identical to the value in ABLR
2. Inside the range bound by ABLR and ABHR inclusive
3. Outside that same range
DRc[4–0]
Bits
2–0
Reset
Field
R/W Write only. ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG
Address Breakpoint Registers (ABLR, ABHR)
Name
TM
instruction and via the BDM port using the
ABLR is accessible in supervisor mode as debug control register 0x0D using the WDEBUG instruction and
via the BDM port using the
31
Transfer modifier. Compared with the local bus transfer modifier signals, which give supplemental
information for each transfer type.
TT = 00 (normal mode):
000 Explicit cache line push
001 User data access
010 User code access
011 Reserved
100 Reserved
101 Supervisor data access
110 Supervisor code access
111 Reserved
TT = 10 (emulator mode):
0xx–100 Reserved
101 Emulator mode data access
110 Emulator mode code access
111 Reserved
TT = 11 (acknowledge/CPU space transfers):
000 CPU space access
001–111 Interrupt acknowledge levels 1–7
These bits also define the TM encoding for BDM memory commands (for backward compatibility).
Figure 30-6. Address Breakpoint Registers (ABLR, ABHR)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 30-5. AATR Field Descriptions (continued)
Figure
WDMREG
30-6, define regions in the processor’s data address space that can
command.
0x0D (ABLR); 0x0C (ABHR)
RDMREG
Address
Description
and
—
WDMREG
commands.
Debug Support
0
30-9