MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 142

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Power Management
7.3.1.2
Wait mode is intended to be used to stop only the CPU and memory clocks until a wakeup event is
detected. In this mode, peripherals may be programmed to continue operating and can generate interrupts,
which cause the CPU to exit from wait mode.
7.3.1.3
Doze mode affects the CPU in the same manner as wait mode, except that each peripheral defines
individual operational characteristics in doze mode. Peripherals which continue to run and have the
capability of producing interrupts may cause the CPU to exit the doze mode and return to run mode.
Peripherals which are stopped will restart operation on exit from doze mode as defined for each peripheral.
7.3.1.4
Stop mode affects the CPU in the same manner as the wait and doze modes, except that all clocks to the
system are stopped and the peripherals cease operation.
Stop mode must be entered in a controlled manner to ensure that any current operation is properly
terminated. When exiting stop mode, most peripherals retain their pre-stop status and resume operation.
The following subsections specify the operation of each module while in and when exiting low-power
modes.
7.3.1.5
Most peripherals may be disabled by software in order to cease internal clock generation and remain in a
static state. Each peripheral has its own specific disabling sequence (refer to each peripheral description
for further details). A peripheral may be disabled at any time and will remain disabled during any
low-power mode of operation.
7.3.2
7.3.2.1
The ColdFire core is disabled during any low-power mode. No recovery time is required when exiting any
low-power mode.
7.3.2.2
SRAM is disabled during any low-power mode. No recovery time is required when exiting any low-power
mode.
7-6
Peripheral Behavior in Low-Power Modes
Wait Mode
Doze Mode
Stop Mode
Peripheral Shut Down
ColdFire Core
Static Random-Access Memory (SRAM)
Entering stop mode will disable the SDRAMC including the refresh counter.
If SDRAM is used, then code is required to insure proper entry and exit from
stop mode. See
information.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Section 7.3.2.5, “SDRAM Controller
NOTE
(SDRAMC)” for more
Freescale Semiconductor