C8051F351-GMR Silicon Laboratories Inc, C8051F351-GMR Datasheet - Page 50

• Manufacturer Part Number: C8051F351-GMR
• Description: IC 8051 MCU 8K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F351-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x24b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F350DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• For Use With: 336-1083 - DEV KIT FOR F350/351/352/353
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F350/1/2/3
50
Bit 7:
Bit 6:
Bits 5–4: RESERVED: Must Write to 00b.
Bit 3:
Bits 2–0: AD0SM: ADC0 System Mode Select.
AD0EN
R/W
Bit7
AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC is in low-power shutdown.
1: ADC0 Enabled. ADC is active and ready to perform calibrations or conversions.
Note: Disabling the ADC automatically resets the AD0SM bits back to the "Idle" state.
Unused: Read = 0b, Write = don’t care.
Unused: Read = 0b, Write = don’t care.
These bits define the operating mode for the ADC. They are used to initiate all ADC conver-
sion and calibration cycles.
000: Idle
001: Full Internal Calibration (offset and gain).
010: Single Conversion.
011: Continuous Conversion.
100: Internal Offset Calibration.
101: Internal Gain Calibration.
110: System Offset Calibration.
111: System Gain Calibration.
Note: Any system mode change by the user during a conversion or calibration will
terminate the operation, and corrupt the result. To write to many of the other ADC reg-
isters, the AD0SM bits must be set to IDLE mode (000b).
Note: During an ADC conversion or calibration, the AD0SM bits may return intermedi-
ate values if they are read. It is not recommended to use these bits as indicator of the
ADC status. Only the ADC0STA register should be used as indicator of the ADC sta-
tus.
Bit6
—
R
Reserved Reserved
SFR Definition 5.3. ADC0MD: ADC0 Mode
R/W
Bit5
R/W
Bit4
Rev. 1.1
Bit3
—
R
R/W
Bit2
AD0SM
R/W
Bit1
SFR Address:
R/W
Bit0
0xF3
00000000
Reset Value