C8051F351-GMR Silicon Laboratories Inc, C8051F351-GMR Datasheet - Page 13

• Manufacturer Part Number: C8051F351-GMR
• Description: IC 8051 MCU 8K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F351-GMR

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x24b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F350DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 24 bit, 8 Channel
• On-chip Dac: 8 bit, 2 Channel
• For Use With: 336-1083 - DEV KIT FOR F350/351/352/353
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

C8051F350/1/2/3
List of Registers
SFR Definition 5.1. ADC0CN: ADC0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
SFR Definition 5.2. ADC0CF: ADC0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SFR Definition 5.3. ADC0MD: ADC0 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SFR Definition 5.4. ADC0CLK: ADC0 Modulator Clock Divisor . . . . . . . . . . . . . . . . . . 51
SFR Definition 5.5. ADC0DECH: ADC0 Decimation Ratio Register High Byte . . . . . . 51
SFR Definition 5.6. ADC0DECL: ADC0 Decimation Ratio Register Low Byte . . . . . . . 52
SFR Definition 5.7. ADC0DAC: ADC0 Offset DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SFR Definition 5.8. ADC0BUF: ADC0 Input Buffer Control . . . . . . . . . . . . . . . . . . . . . 53
SFR Definition 5.9. ADC0STA: ADC0 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SFR Definition 5.10. ADC0COH: ADC0 Offset Calibration Register High Byte . . . . . . 55
SFR Definition 5.11. ADC0COM: ADC0 Offset Calibration Register Middle Byte . . . . 55
SFR Definition 5.12. ADC0COL: ADC0 Offset Calibration Register Low Byte . . . . . . . 55
SFR Definition 5.13. ADC0CGH: ADC0 Gain Calibration Register High Byte . . . . . . . 56
SFR Definition 5.14. ADC0CGM: ADC0 Gain Calibration Register Middle Byte . . . . . 56
SFR Definition 5.15. ADC0CGL: ADC0 Gain Calibration Register Low Byte . . . . . . . . 56
SFR Definition 5.16. ADC0H: ADC0 Conversion Register (SINC3 Filter) High Byte . . 57
SFR Definition 5.17. ADC0M: ADC0 Conversion Register (SINC3 Filter) Middle Byte 57
SFR Definition 5.18. ADC0L: ADC0 Conversion Register (SINC3 Filter) Low Byte . . . 57
SFR Definition 5.19. ADC0FH: ADC0 Conversion Register (Fast Filter) High Byte . . . 58
SFR Definition 5.20. ADC0FM: ADC0 Conversion Register (Fast Filter) Middle Byte . 58
SFR Definition 5.21. ADC0FL: ADC0 Conversion Register (Fast Filter) Low Byte . . . . 58
SFR Definition 5.22. ADC0MUX: ADC0 Analog Multiplexer Control . . . . . . . . . . . . . . 60
SFR Definition 6.1. IDA0CN: IDA0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 6.2. IDA0: IDA0 Data Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SFR Definition 6.3. IDA1CN: IDA1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SFR Definition 6.4. IDA1: IDA1 Data Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SFR Definition 7.1. REF0CN: Reference Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SFR Definition 9.1. CPT0CN: Comparator0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
SFR Definition 9.2. CPT0MD: Comparator0 Mode Selection . . . . . . . . . . . . . . . . . . . . 82
SFR Definition 9.3. CPT0MX: Comparator0 MUX Selection . . . . . . . . . . . . . . . . . . . . 84
SFR Definition 10.1. SP: Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 10.2. DPL: Data Pointer Low Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 10.3. DPH: Data Pointer High Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
SFR Definition 10.4. PSW: Program Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
SFR Definition 10.5. ACC: Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 10.6. B: B Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SFR Definition 10.7. PCON: Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SFR Definition 12.1. IE: Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SFR Definition 12.2. IP: Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
SFR Definition 12.3. EIE1: Extended Interrupt Enable 1 . . . . . . . . . . . . . . . . . . . . . . 109
SFR Definition 12.4. EIP1: Extended Interrupt Priority 1 . . . . . . . . . . . . . . . . . . . . . . 110
SFR Definition 12.5. IT01CF: INT0/INT1 Configuration . . . . . . . . . . . . . . . . . . . . . . . 112
SFR Definition 13.1. PFE0CN: Prefetch Engine Control . . . . . . . . . . . . . . . . . . . . . . 113
Rev. 1.1
13