ST72F623F2M1 STMicroelectronics, ST72F623F2M1 Datasheet - Page 89

• Manufacturer Part Number: ST72F623F2M1
• Description: IC MCU 8BIT LS 8K 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F623F2M1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-2114-5

USB INTERFACE (Cont’d)
10.6.5 Programming Considerations
The interaction between the USB interface and the
application program is described below. Apart
from system reset, action is always initiated by the
USB interface, driven by one of the USB events
associated with the Interrupt Status Register (IS-
TR) bits.
10.6.5.1 Initializing the Registers
At system reset, the software must initialize all reg-
isters to enable the USB interface to properly gen-
erate interrupts and DMA requests.
1. Initialize the DMAR, IDR, and IMR registers
2. Initialize the EP0RA and EP0RB registers to
3. When addresses are received through this
4. If needed, write the endpoint numbers in the EA
10.6.5.2 Initializing DMA buffers
The DMA buffers are a contiguous zone of memo-
ry whose maximum size is 48 bytes. They can be
placed anywhere in the memory space to enable
the reception of messages. The 10 most signifi-
cant bits of the start of this memory area are spec-
ified by bits DA15-DA6 in registers DMAR and
IDR, the remaining bits are 0. The memory map is
shown in
Each buffer is filled starting from the bottom (last 3
address bits=000) up.
10.6.5.3 Endpoint Initialization
To be ready to receive:
Set STAT_RX to VALID (11b) in EP0RB to enable
reception.
To be ready to transmit:
1. Write the data in the DMA transmit buffer.
2. In register EPnRA, specify the number of bytes
3. Enable the endpoint by setting the STAT_TX
Note: Once transmission and/or reception are en-
abled, registers EPnRA and/or EPnRB (respec-
tively) must not be modified by software, as the
hardware can change their value on the fly.
(choice of enabled interrupts, address of DMA
buffers). Refer the paragraph titled initializing
the DMA Buffers.
enable accesses to address 0 and endpoint 0
to support USB enumeration. Refer to the para-
graph titled Endpoint Initialization.
channel, update the content of the DADDR.
fields in the EP1RB and EP2RB register.
to be transmitted in the TBC field
bits to VALID (11b) in EPnRA.
Figure
51.
Doc ID 6996 Rev 5
When the operation is completed, they can be ac-
cessed again to enable a new operation.
10.6.5.4 Interrupt Handling
Start of Frame (SOF)
The interrupt service routine may monitor the SOF
events for a 1 ms synchronization event to the
USB bus. This interrupt is generated at the end of
a resume sequence and can also be used to de-
tect this event.
USB Reset (RESET)
When this event occurs, the DADDR register is re-
set, and communication is disabled in all endpoint
registers (the USB interface will not respond to any
packet). Software is responsible for reenabling
endpoint 0 within 10 ms of the end of reset. To do
this, set the STAT_RX bits in the EP0RB register
to VALID.
Suspend (SUSP)
The CPU is warned about the lack of bus activity
for more than 3 ms, which is a suspend request.
The software should set the USB interface to sus-
pend mode and execute an ST7 HALT instruction
to meet the USB-specified power constraints.
End Suspend (ESUSP)
The CPU is alerted by activity on the USB, which
causes an ESUSP interrupt. The ST7 automatical-
ly terminates HALT mode.
Correct Transfer (CTR)
1. When this event occurs, the hardware automat-
2. Read the PIDR to obtain the token and the IDR
3. Clear the CTR bit in the ISTR register.
ically sets the STAT_TX or STAT_RX to NAK.
Note: Every valid endpoint is NAKed until soft-
ware clears the CTR bit in the ISTR register,
independently
addressed by the transfer which generated the
CTR interrupt.
Note: If the event triggering the CTR interrupt is
a SETUP transaction, both STAT_TX and
STAT_RX are set to NAK.
to get the endpoint number related to the last
transfer.
Note: When a CTR interrupt occurs, the TP3-
TP2 bits in the PIDR register and EP1-EP0 bits
in the IDR register stay unchanged until the
CTR bit in the ISTR register is cleared.
of
the
endpoint
number
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