ST72F623F2M1 STMicroelectronics, ST72F623F2M1 Datasheet - Page 57

• Manufacturer Part Number: ST72F623F2M1
• Description: IC MCU 8BIT LS 8K 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F623F2M1

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 3x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST72F6x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SCI, SPI, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 2
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-2114-5

SERIAL PERIPHERAL INTERFACE (Cont’d)
10.4.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
Figure 40. Single Master/ Single Slave Application
40.
MSBit
8-BIT SHIFT REGISTER
GENERATOR
CLOCK
SPI
MASTER
LSBit
SCK
MOSI
SS
MISO
Doc ID 6996 Rev 5
+5V
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins
must be connected at each node (in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see
must be programmed with the same timing mode.
MOSI
MISO
SCK
SS
Figure
8-BIT SHIFT REGISTER
MSBit
Not used if SS is managed
by software
43) but master and slave
SLAVE
ST7262xxx
LSBit
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