M30873FHBGP#U3 Renesas Electronics America, M30873FHBGP#U3 Datasheet - Page 442

• Manufacturer Part Number: M30873FHBGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30873FHBGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 418 of 587
Figure 23.12
Figure 23.13
23.1.9
23.1.10 CANi Receive Error Count Register (CiREC Register) (i = 0, 1)
CANi Transmit Error Count Register (i = 0, 1)
CANi Receive Error Count Register (i = 0, 1)
b7
b7
In an error active and an error passive state, a transmit error count value is stored into the CiTEC register. The
count is decremented when a transmit operation is successfully completed and incremented when a transmit
error occurs.
In a bus-off state, the value in the CiTEC register is undefined. The CiTEC register becomes 00h when the
CAN module is placed in an error active state again.
In an error active and an error passive state, a receive error count value is stored into the CiREC register. The
count is decremented when a receive operation is successfully completed and incremented when a receive error
occurs.
The CiREC register becomes 127 when a receive operation is successfully completed while the CiREC register
equals or exceeds 128 (in an error passive state).
In a bus-off state, the value in the CiREC register is undefined. The CiREC register becomes 00h when the
CAN module is placed in an error active state again.
NOTE:
NOTE:
1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the clock
1. The value is obtained by setting the SLEEP bit in the CiSLPR register to 1 (sleep mode exited) after reset and supplying the
to the CAN module.
clock to the CAN module.
CANi Transmit Error Count Register (CiTEC Register) (i = 0, 1)
C0TEC and C1TEC Registers
C0REC and C1REC Registers
b0
b0
Transmit error count value
Receive error count value
Symbol
C0TEC
C1TEC
Symbol
C0REC
C1REC
Address
020Ah
028Ah
Address
020Bh
028Bh
Function
Function
After Reset
00h
00h
After Reset
00h
00h
23. CAN Module
(1)
(1)
RW
RW
RO
RO