M30873FHBGP#U3 Renesas Electronics America, M30873FHBGP#U3 Datasheet - Page 305

• Manufacturer Part Number: M30873FHBGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30873FHBGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 281 of 587
Figure 17.47
j = 1, k = 0 when i = 5, j = 10, k = 9 when i = 6
The above applies under the following conditions:
NOTE:
Internal clock
TE bit in the
UiC1 register
TI bit in the UiC1
register
CTSi Input
CLKi output
TXDi output
TXEP bit in the
UiC0 register
UiTR bit in the
IIOjIR register
RXDi input
RI bit in the
UiC1 register
UiRR bit in the
IIOkIR register
- UiMR register: CKDIR bit = 0 (internal clock)
- UiC0 register: CRD bit in the = 0 and CRS bit = 0 (CTS function used)
- U56CON register: UiIRS bit = 0 (Transmit interrupt request is generated when no data in the UiTB register)
1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).
Transmit and Receive Operation when Internal Clock is Selected
CKPOL bit = 0 (transmit data output at the falling edge of the serial clock)
“H”
“L”
“H”
“L”
“H”
“L”
“H”
“L”
1
0
1
0
1
0
1
0
1
0
1
0
Transfer data from UARTi
receive shift register to UiRB
register
Write data to the UiTB register
D0
D0 D1 D2 D3 D4 D5 D6
TC
Transfer data from UiTB register
to UARTi transmit shift register
D1 D2 D3 D4 D5 D6
TCLK
Set to 0 by an interrupt request acknowledgement or by a program
Set to 0 by an interrupt request acknowlegement or by a program
D7
D7
Communication stops
because CTSi = "H"
A read from the UiRB register
D0 D1 D2 D3 D4 D5 D6
D0 D1 D2 D3 D4 D5 D6
17. Serial Interfaces (UART5 and UART6)
D7
D7
TC = TCLK =
fj = f1, f8, f2n
m = Setting value of the UiBRG register
Communication stops because
TE bit = 0
(00h to FFh)
D0 D1 D2 D3 D4 D5
D0 D1 D2 D3 D4 D5
(1)
2(m + 1)
fj