M30873FHBGP#U3 Renesas Electronics America, M30873FHBGP#U3 Datasheet - Page 308

• Manufacturer Part Number: M30873FHBGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30873FHBGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ09B0180-0151 Rev.1.51 Jul 31, 2008
Page 284 of 587
Figure 17.50
17.2.1.2 LSB First or MSB First
17.2.1.3 Continuous Receive Mode
As shown in Figure 17.50, the UFORM bit in the UiC0 register (i = 5, 6) determines a bit order.
Continuous receive mode can be used when all of the following conditions are met.
When the UiRRM bit in the U56CON register is set to 1 (continuous receive mode enabled), the TI bit in the
UiC1 register becomes 0 (data in the UiTB register) by reading the UiRB register. Do not set dummy data to
the UiTB register if the UiRRM bit is set to 1.
•
•
External clock is selected (the CKDIR bit in the UiMR register (i = 5 and 6) is set to 1)
RTS function is disabled (RTSi pin is not selected in the Function Select Register)
(1) When the UFORM bit in the UiC0 register (i = 5, 6) is set to 0 (LSB first)
(2) When the UFORM bit is set to 1 (MSB first)
CLKi
TXDi
RXDi
CLKi
TXDi
RXDi
Bit order (8-Bit Data Length)
The above applies under the following conditions:
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
- UiC0 register: CKPOL bit = 0 (transmit data is output at the falling edge of the serial clock and
received data is input at the rising edge).
D0
D0
D7
D7
D1
D1
D6
D6
D2
D2
D5
D5
D3
D3
D4
D4
D4
D4
D3
D3
17. Serial Interfaces (UART5 and UART6)
D5
D5
D2
D2
D6
D6
D1
D1
D7
D7
D0
D0