PIC16F785-I/SO Microchip Technology, PIC16F785-I/SO Datasheet - Page 64

IC PIC MCU FLASH 2KX14 20SOIC

PIC16F785-I/SO

Manufacturer Part Number
PIC16F785-I/SO
Description
IC PIC MCU FLASH 2KX14 20SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F785-I/SO

Program Memory Type
FLASH
Program Memory Size
3.5KB (2K x 14)
Package / Case
20-SOIC (7.5mm Width)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
RS- 232/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
17
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029
Minimum Operating Temperature
- 40 C
On-chip Adc
14-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOICXLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC162060 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F785-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16F785/HV785
8.3.3
In Sleep mode, all clock sources are disabled. Timer2
will not increment and the state of the module will not
change. If the RC5/CCP1 pin is driving a value, it will
continue to drive that value. When the device wakes
up, it will continue from this state.
8.3.3.1
If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the CCP to be clocked from the internal
oscillator clock source, which may have a different
clock frequency than the primary clock.
See Section 3.0 “Clock Sources” for additional
details.
8.3.4
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
TABLE 8-4:
DS41249E-page 62
Name
CCP1CON
CCPR1L
CCPR1H
INTCON
PIE1
PIR1
PR2
T2CON
TMR2
TRISC
Legend:
– = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the CCP or Timer2 modules.
OPERATION IN SLEEP MODE
EFFECTS OF RESET
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
Timer2 Module Period Register
Timer2 Module Register
OPERATION WITH FAIL-SAFE
CLOCK MONITOR
TRISC7
EEIE
EEIF
Bit 7
GIE
REGISTERS ASSOCIATED WITH CCP AND TIMER2
TOUTPS3 TOUTPS2
TRISC6
PEIE
ADIE
ADIF
Bit 6
CCP1IE
CCP1IF
TRISC5
DC1B1
Bit 5
T0IE
TOUTPS1
TRISC4
DC1B0
INTE
C2IE
Bit 4
C2IF
TOUTPS0
CCP1M3
TRISC3
RAIE
Bit 3
C1IE
C1IF
TMR2ON
CCP1M2
TRISC2
OSFIE
8.3.5
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
5.
6.
OSFIF
Bit 2
T0IF
Configure the PWM pin (RC5/CCP1) as an input
by setting the TRISC<5> bit.
Set the PWM period by loading the PR2 register.
Configure the CCP module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
• Set the TMR2 prescale value by loading the
• Enable Timer2 by setting the TMR2ON bit of
Enable PWM output after a new PWM cycle has
started:
• Wait until TMR2 overflows (TMR2IF bit is
• Enable the RC5/CCP1 pin output by clearing
set).
the TRISC<5> bit.
the TMR2IF bit of the PIR1 Register.
T2CKPS bits of the T2CON Register.
the T2CON Register.
T2CKPS1
CCP1M1
TMR2IE
TMR2IF
TRISC1
Bit 1
INTF
SETUP FOR PWM OPERATION
T2CKPS0
CCP1M0
TMR1IE
TMR1IF
TRISC0
RAIF
Bit 0
© 2008 Microchip Technology Inc.
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
1111 1111
-000 0000
0000 0000
--11 1111
POR, BOR
Value on
other Resets
Value on all
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
0000 0000
1111 1111
-000 0000
0000 0000
--11 1111

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