PIC16F785-I/SO Microchip Technology, PIC16F785-I/SO Datasheet
PIC16F785-I/SO
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PIC16F785-I/SO Summary of contents
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... Two-Phase Asynchronous Feedback PWM Dual High-Speed Comparators and © 2008 Microchip Technology Inc. PIC16F785/HV785 Data Sheet 20-Pin Flash-Based, 8-Bit CMOS Microcontroller with Dual Operational Amplifiers DS41249E ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... MHz, 2.0V, typical • Watchdog Timer Current μA @ 2.0V, typical • Timer1 Oscillator Current μ kHz, 2.0V, typical © 2008 Microchip Technology Inc. PIC16F785/HV785 Peripheral Features: • High-Speed Comparator module with: - Two independent analog comparators - Programmable on-chip voltage reference (CV ...
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... PIC16F785/HV785 Program Data Memory Memory Device Flash SRAM EEPROM (words) (bytes) (bytes) PIC16F785 2048 128 256 PIC16HV785 2048 128 256 Dual in Line Pin Diagram 20-pin PDIP, SOIC, SSOP RA5/T1CKI/OSC1/CLKIN RA4/AN3/T1G/OSC2/CLKOUT RA3/MCLR/V RC5/CCP1 RC4/C2OUT/PH2 RC3/AN7/C12IN3-/OP1 RC6/AN8/OP1- RC7/AN9/OP1+ RB7/SYNC TABLE 1: DUAL IN LINE PIN SUMMARY ...
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... Note 1: Input only. 2: Open drain. © 2008 Microchip Technology Inc. PIC16F785/HV785 RA1/AN1/C12IN0-/ RA2/AN2/T0CKI/INT/C1OUT 14 RC0/AN4/C2IN RC1/AN5/C12IN1-/PH1 RC2/AN6/C12IN2-/OP2 PIC16F785/HV785 Op PWM Timers CCP Amps — — — — — — — — — — T0CKI — — — — — — ...
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... PIC16F785/HV785 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................... 9 3.0 Clock Sources ............................................................................................................................................................................ 23 4.0 I/O Ports ..................................................................................................................................................................................... 35 5.0 Timer0 Module ........................................................................................................................................................................... 49 6.0 Timer1 Module with Gate Control............................................................................................................................................... 51 7.0 Timer2 Module ........................................................................................................................................................................... 55 8.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 57 9.0 Comparator Module.................................................................................................................................................................... 63 10.0 Voltage References .................................................................................................................................................................... 70 11.0 Operational Amplifier (OPA) Module .......................................................................................................................................... 75 12 ...
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... DEVICE OVERVIEW This document contains device specific information for the PIC16F785/HV785 available in 20-pin PDIP, SOIC, SSOP and QFN packages. Figure 1-1 shows a block diagram of the PIC16F785/HV785 device. Table 1-1 shows the pinout description. FIGURE 1-1: PIC16F785/HV785 BLOCK DIAGRAM Configuration Flash ...
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... PIC16F785/HV785 TABLE 1-1: PIC16F785/HV785 PINOUT DESCRIPTION Name Function RA0/AN0/C1IN+/ICSPDAT RA0 AN0 C1IN+ ICSPDAT RA1/AN1/C12IN0-/V / RA1 REF ICSPCLK AN1 C12IN0- V REF ICSPCLK RA2/AN2/T0CKI/INT/C1OUT RA2 AN2 T0CKI INT C1OUT RA3/MCLR/Vpp RA3 MCLR V PP RA4/AN3/T1G/OSC2/ RA4 CLKOUT AN3 T1G OSC2 CLKOUT RA5/T1CKI/OSC1/CLKIN RA5 ...
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... TABLE 1-1: PIC16F785/HV785 PINOUT DESCRIPTION (CONTINUED) Name Function RC1/AN5/C12IN1-/PH1 RC1 AN5 C12IN1- PH1 RC2/AN6/C12IN2-/OP2 RC2 AN6 C12IN2- OP2 RC3/AN7/C12IN3-/OP1 RC3 AN7 C12IN3- OP1 RC4/C2OUT/PH2 RC4 C2OUT PH2 RC5/CCP1 RC5 CCP1 RC6/AN8/OP1- RC6 AN8 OP1- RC7/AN9/OP1+ RC7 AN9 OP1+ ...
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... PIC16F785/HV785 NOTES: DS41249E-page 8 © 2008 Microchip Technology Inc. ...
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... MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC16F785/HV785 has a 13-bit program counter capable of addressing program memory space. Only the first (0000h-07FFh) for the PIC16F785/HV785 is physically implemented. Access- ing a location above these boundaries will cause a wrap around within the first space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 2-1) ...
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... PIC16F785/HV785 FIGURE 2-2: DATA MEMORY MAP OF THE PIC16F785/HV785 File Address (1) Indirect addr. 00h Indirect addr. TMR0 01h OPTION_REG 81h PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC 08h 09h PCLATH 0Ah ...
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... TABLE 2-2: PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 Module’s Register 02h PCL Program Counter’s (PC) Least Significant Byte ...
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... PIC16F785/HV785 TABLE 2-3: PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1 Addr Name Bit 7 Bit 6 Bank 1 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RAPU INTEDG 82h PCL Program Counter’s (PC) Least Significant Byte 83h ...
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... TABLE 2-4: PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2 Addr Name Bit 7 Bit 6 Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 101h TMR0 Timer0 Module’s Register 102h PCL Program Counter’s (PC) Least Significant Byte ...
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... PIC16F785/HV785 TABLE 2-5: PIC16F785/HV785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3 Addr Name Bit 7 Bit 6 Bank 3 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) OPTION_RE 181h RAPU INTEDG G 182h PCL Program Counter’s (PC) Least Significant Byte 183h ...
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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2008 Microchip Technology Inc. PIC16F785/HV785 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged) ...
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... Note 1: A dedicated 16-bit WDT postscaler is available for the PIC16F785/HV785. See Section 15.5 “Watchdog Timer (WDT)” for more information. DS41249E-page 16 Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT by setting PSA bit to ‘1’ in the OPTION Reg- ister. See Section 5.4 “ ...
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... Note 1: IOCA register must also be enabled. 2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before clear- ing T0IF bit. © 2008 Microchip Technology Inc. PIC16F785/HV785 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE bit of the INTCON register ...
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... PIC16F785/HV785 2.2.2.4 PIE1 Register The Peripheral Interrupt Enable Register 1 contains the interrupt enable bits, as shown in Register 2-4. REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 EEIE ADIE CCP1IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ...
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... TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Timer1 register overflowed (must be cleared in software Timer1 has not overflowed © 2008 Microchip Technology Inc. PIC16F785/HV785 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE, in the INTCON Register) ...
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... PIC16F785/HV785 2.2.2.6 PCON Register The Power Control register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Timer (WDT) Reset (WDT) and an external MCLR Reset. REGISTER 2-6: PCON: POWER CONTROL REGISTER U-0 U-0 U-0 — — bit 7 ...
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... PCLATH 2.3.3 STACK Program The PIC16F785/HV785 family has an 8-level deep x 13-bit wide hardware stack (see Figure 2-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...
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... Writing to the INDF register indirectly results operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit in the STATUS Register, as shown in Figure 2-4. FIGURE 2-4: DIRECT/INDIRECT ADDRESSING PIC16F785/HV785 Direct Addressing From Opcode RP1RP0 6 Bank Select ...
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... CLOCK SOURCES 3.1 Overview The PIC16F785/HV785 has a wide variety of clock sources and selection features to allow used in a wide range of applications while maximizing perfor- mance and minimizing power consumption. Figure 3-1 illustrates a block diagram of the PIC16F785/HV785 clock sources. Clock sources can be configured from external oscilla- tors, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits ...
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... The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is pro- viding a stable system clock to the PIC16F785/HV785. Table 3-1 shows examples where the oscillator delay is invoked. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 3.6 “ ...
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... HS 4.0 MHz 8.0 MHz 16.0 MHz Note: These values are for design guidance only. See notes following this table. Sleep To Internal Logic vary CERAMIC RESONATOR OPERATION ( MODE) PIC16F785/HV785 OSC1 Sleep P ( OSC2 S ( Internal Logic ) may be required for S varies with the Oscillator ...
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... The user also needs to take into account EXT variation due to tolerance of external RC components used. Internal Clock ≥ 3.0V) DD < 3.0V) DD RCIO MODE Internal OSC1 Clock PIC16F785/HV785 I/O (OSC2) ≤ 100 kΩ (V ≥ 3.0V) EXT DD 10 kΩ ≤ R ≤ 100 kΩ (V < 3.0V) EXT DD C > EXT ...
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... Internal Clock Modes The PIC16F785/HV785 has two independent, internal oscillators that can be configured or selected as the system clock source. 1. The HFINTOSC (High-frequency Internal Oscil- lator) is factory calibrated and operates at 8 MHz. The frequency of the HFINTOSC can be user adjusted ±12% via software using the OSCTUNE register (Register 3-1) ...
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... PIC16F785/HV785 3.4.2.2 OSCTUNE Register The HFINTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 3-1). The OSCTUNE register has a nominal tuning range of ±12%. The default value of the OSCTUNE register is ‘0’. The value is a 5-bit two’s complement number. Due to process variation, the monotonicity and frequency step cannot be specified ...
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... Following any Reset, the IRCF bits are set to ‘110’ and the frequency selection is forced to 4 MHz. The user can modify the IRCF bits to select a different frequency. © 2008 Microchip Technology Inc. PIC16F785/HV785 3.4.5 HF AND LF INTOSC CLOCK SWITCH TIMING When switching between the LFINTOSC and the HFIN- TOSC, the new oscillator may already be shut down to save power. If this is the case, there μ ...
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... System clock is switched to external clock source. 3.6.3 CHECKING EXTERNAL/INTERNAL CLOCK STATUS Checking the state of the OSTS bit in the OSCCON Register) will confirm if the PIC16F785/HV785 is run- ning from the external clock source as defined by the F bits in the Configuration Word (CONFIG) or the OSC internal oscillator. ...
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... OSFIE bit in the PIE1 Reg- ister is set. The device will then switch the system clock to the internal oscillator. The system clock will continue to come from the internal oscillator unless the external clock recovers and the Fail-Safe condition is exited. © 2008 Microchip Technology Inc. PIC16F785/HV785 ...
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... The Fail-Safe condition is cleared after a Reset, the execution of a SLEEP instruction modification of the SCS bit. While in Fail-Safe condition, the PIC16F785/HV785 uses the internal oscillator as the system clock source. The IRCF bits in the OSCCON Register can be modified to adjust the internal oscillator frequency without exiting the Fail-Safe condition. ...
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... Internal oscillator is used for system clock 0 = Clock source defined by FOSC<2:0> Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP selected as the Oscillator mode or Fail-Safe mode is enabled, otherwise this bit resets to ‘1’ © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R-q R-0 (1) ...
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... PIC16F785/HV785 TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Name Bit 7 Bit 6 Bit 5 CONFIG CPD CP MCLRE OSCCON — IRCF2 IRCF1 OSCTUNE — — — PIE1 EEIE ADIE CCP1IE PIR1 EEIF ADIF CCP1IF Legend unknown unchanged, – = unimplemented locations read as ‘0’ value depends on condition. Shaded cells are not used by oscillators ...
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... Note 1: Data latches are unknown after a POR, but each port bit reads ‘0’ when the corresponding analog select bit is ‘1’ (see Register 12-1). © 2008 Microchip Technology Inc. PIC16F785/HV785 The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs ...
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... Note 1: TRISA<3> always reads ‘1’. 2: TRISA<5:4> always reads ‘1’ in XT, HS and LP OSC modes. 4.2 Additional Pin Functions Every PORTA pin on the PIC16F785/HV785 has an interrupt-on-change option and a weak pull-up option. The next three sections describe these functions. REGISTER 4-3: WPUA: WEAK PULL-UP REGISTER ...
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... Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be recognized. 2: IOCA<5:4> always reads ‘1’ in XT, HS and LP OSC modes. © 2008 Microchip Technology Inc. PIC16F785/HV785 This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, clears the inter- ...
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... PIC16F785/HV785 4.2.3 PORTA PIN DESCRIPTIONS AND DIAGRAMS Each PORTA pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individ- ual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. ...
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... Change RD PORTA To TMR0 To INT To A/D Converter © 2008 Microchip Technology Inc. PIC16F785/HV785 4.2.3.4 Figure 4-4 shows the diagram for this pin. The RA3 pin is configurable to function as one of the following: • General purpose input • Master Clear Reset with weak pull-up FIGURE 4-4: ...
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... PIC16F785/HV785 4.2.3.5 RA4/AN3/T1G/OSC2/CLKOUT Figure 4-5 shows the diagram for this pin. The RA4 pin is configurable to function as one of the following: • General purpose I/O • Analog input for the A/D • TMR1 gate input • Crystal/resonator connection • Clock output FIGURE 4-5: ...
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... TMR1GE T1CKPS1 TRISA — — TRISA5 WPUA — — WPUA5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. © 2008 Microchip Technology Inc. PIC16F785/HV785 Bit 4 Bit 3 Bit 2 Bit 1 ANS4 ANS3 ANS2 ANS1 C1POL C1SP C1R C1CH1 — ...
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... PIC16F785/HV785 4.3 PORTB and TRISB Registers PORTB is a 4-bit wide, bidirectional port. The corre- sponding data direction register is TRISB (Register 4- 6). Setting a TRISB bit (= 1) will make the correspond- ing PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
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... CK Q PORTB TRISB ANS10 (RB4) ANS11 (RB5) RD TRISB PORTB To A/D Converter To Op Amp 2 © 2008 Microchip Technology Inc. PIC16F785/HV785 4.3.1.3 RB6 The RB6 pin is configurable to function as the following: • Open drain general purpose I/O FIGURE 4-8: Data Bus PORTB TRISB RD TRISB ...
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... PIC16F785/HV785 TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 Bit 5 ANSEL1 — — — OPA2CON OPAON — — PORTB RB7 RB6 RB5 PWMCON0 PRSEN PASEN BLANK2 TRISB TRISB7 TRISB6 TRISB5 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. ...
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... TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated PORTC pin configured as an output © 2008 Microchip Technology Inc. PIC16F785/HV785 When RC4 or RC5 is configured amp output, the corresponding RC4 or RC5 digital output driver will automatically be disabled regardless of the TRISC<4> ...
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... PIC16F785/HV785 4.4.1 PORTC PIN DESCRIPTIONS AND DIAGRAMS Each PORTC pin is multiplexed with other functions. The pins and their combined functions are briefly described here. For specific information about individ- ual functions such as the comparator or the A/D, refer to the appropriate section in this Data Sheet. ...
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... ANS7 (RC3) RD TRISC PORTC To Comparators To A/D Converter © 2008 Microchip Technology Inc. PIC16F785/HV785 4.4.1.7 RC4/C2OUT/PH2 The RC4 is configurable to function as one of the following: • General purpose I/O • Digital output from Comparator 2 • Digital output from the Two-Phase PWM FIGURE 4-13: C2OE PH2EN ...
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... PIC16F785/HV785 4.4.1.8 RC5/CCP1 The RC5 is configurable to function as one of the following: • General purpose I/O • Digital input for the capture/compare • Digital output for the CCP TABLE 4-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 Bit 5 ANSEL1 — — — ...
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... Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG (see Register 2.2.2.3). 2: WDTPS<3:0> are bits in the WDTCON register (see Register 15-2). © 2008 Microchip Technology Inc. PIC16F785/HV785 RA2/AN2/T0CKI/INT/C1OUT. The incrementing edge is determined by the source edge (T0SE) control bit of the OPTION Register. Clearing the T0SE bit selects the rising edge ...
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... PIC16F785/HV785 5.3 Using Timer0 with an External Clock When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accom- plished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore ...
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... TIMER1 MODULE WITH GATE CONTROL The Timer1 module is the 16-bit counter of the PIC16F785/HV785. Figure 6-1 shows the basic block diagram of the Timer1 module. Timer1 has the follow- ing features: • 16-bit timer/counter (TMR1H:TMR1L) • Readable and writable • Internal or external clock selection • ...
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... PIC16F785/HV785 6.1 Timer1 Modes of Operation Timer1 can operate in one of three modes: • 16-bit Timer with prescaler • 16-bit Synchronous counter • 16-bit Asynchronous counter In Timer mode, Timer1 is incremented on every instruc- tion cycle. In Counter mode, Timer1 is incremented on the rising edge of the external clock input T1CKI. In ...
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... Enables Timer1 0 = Stops Timer1 Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source. 2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by T1GSS bit (CM2CON1<1>), as a Timer1 gate source. © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 T1CKPS0 T1OSCEN T1SYNC U = Unimplemented bit, read as ‘ ...
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... PIC16F785/HV785 6.5 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC of the T1CON Register is set, the external clock input is not synchronized. The timer con- tinues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake- up the processor ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2008 Microchip Technology Inc. PIC16F785/HV785 7.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module ...
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... PIC16F785/HV785 7.2 Timer2 Interrupt The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. FIGURE 7-1: ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. © 2008 Microchip Technology Inc. PIC16F785/HV785 TABLE 8-1: CCP MODE – TIMER RESOURCES REQUIRED ...
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... PIC16F785/HV785 8.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC5/CCP1. An event is defined as one of the following and is configured by CCP1CON<3:0>: • Every falling edge • Every rising edge • Every 4th rising edge • Every 16th rising edge When a capture is made, the interrupt request flag bit CCP1IF of the PIR1 Register is set ...
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... TRISC5 Legend: – = Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by the Capture, Compare or Timer1 module. © 2008 Microchip Technology Inc. PIC16F785/HV785 8.2.4 SPECIAL EVENT TRIGGER In this mode (CCP1M<3:0> = 1011), an internal hardware trigger is generated, which may be used to initiate an action ...
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... PIC16F785/HV785 8.3 CCP PWM Mode In Pulse Width Modulation (PWM) mode, the CCP module produces 10-bit resolution PWM output on the RC5/CCP1 pin. Since the RC5/CCP1 pin is multiplexed with the PORTC data latch, the TRISC<5> must be cleared to make the RC5/CCP1 pin an output. Note: ...
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... Maximum Resolution (bits) 10 Note 1: Changing duty cycle will cause a glitch. © 2008 Microchip Technology Inc. PIC16F785/HV785 CCPR1L and DC1B<1:0> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i ...
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... PIC16F785/HV785 8.3.3 OPERATION IN SLEEP MODE In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change. If the RC5/CCP1 pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. ...
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... Note: To use AN<7:5,1> as analog inputs the appropriate bits must be programmed to ‘1’ in the ANSEL0 register. © 2008 Microchip Technology Inc. PIC16F785/HV785 Setting C1R of the CM1CON0 Register selects the C1V output of the comparator voltage reference REF module as the reference voltage for the comparator. ...
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... PIC16F785/HV785 FIGURE 9-1: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> RA1/AN1/C12IN0-/V /ICSPCLK REF RC1/AN5/C12IN1-/PH1 RC2/AN6/C12IN2-/OP2 RC3/AN7/C12IN3-/OP1 C1R RA0/AN0/C1IN+/ICSPDAT C1V REF Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. 2: Output shown for reference only. For more detail, see Figure 4-3. ...
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... C1VN of C1 connects to RA1/AN1/C12IN0-/ C1VN of C1 connects to RC1/AN5/C12IN1-/PH1 10 = C1VN of C1 connects to RC2/AN6/C12IN2-/OP2 11 = C1VN of C1 connects to RC3/AN7/C12IN3-/OP1 Note 1: C1OUT will only drive RA2/AN2/T0CKI/INT/C1OUT if: (C1OE = 1) and (C1ON = 1) and (TRISA<2> = 0). © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 C1POL C1SP C1R U = Unimplemented bit, read as ‘ ...
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... PIC16F785/HV785 9.1.2 COMPARATOR C2 CONTROL REGISTERS The CM2CON0 register is a functional copy of the CM1CON0 register described in Section 9.1.1 “Com- parator C1 Control Register”. A second control regis- ter, CM2CON1, is also present for control of an additional synchronizing feature, as well as mirrors of both comparator outputs. 9.1.2.1 ...
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... C2VN of C2 connects to RA1/AN1/C12IN0-/ C2VN of C2 connects to RC1/AN5/C12IN1-/PH1 10 = C2VN of C2 connects to RC2/AN6/C12IN2-/OP2 11 = C2VN of C2 connects to RC3/AN7/C12IN3-/OP1 Note 1: C2OUT will only drive RC4/C2OUT/PH2 if: (C2OE = 1) and (C2ON = 1) and (TRISC<4> = 0). © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 C2POL C2SP C2R U = Unimplemented bit, read as ‘ ...
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... PIC16F785/HV785 9.1.2.2 Control Register CM2CON1 Comparator C2 has one additional feature: its output can be synchronized to the Timer1 clock input. Setting C2SYNC of the CM2CON1 Register synchronizes the output of Comparator 2 to the falling edge of the Timer1 clock input (see Figure 9-2 and Register 9-3). ...
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... CxIF bits will still be set if an interrupt con- dition occurs. The comparator interrupt of the PIC16F785/HV785 differs from previous designs in that the interrupt flag is set by the mismatch edge and not the mismatch level. ...
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... PIC16F785/HV785 10.0 VOLTAGE REFERENCES There are two voltage references available in the PIC16F785/HV785: The voltage referred to as the comparator reference ( variable voltage REF based The voltage referred to as the VR refer- DD ence (VR fixed voltage derived from a stable band gap source. Each source may be individually routed ...
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... COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM 16-1 Analog (1) CVREN CV REF CVROE C1VREN C1V to REF 1 Comparator 1 Input 0 C2VREN C2V to REF 1 Comparator 2 Input 0 Note 1: See Register 10-1, bits 3-0. © 2008 Microchip Technology Inc. PIC16F785/HV785 16 Stages MUX 15 · · · 0 VR3:VR0 VR 1 VRR DS41249E-page 71 ...
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... PIC16F785/HV785 REGISTER 10-1: VRCON: VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 R/W-0 (1) (1) C1VREN C2VREN VRR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 C1VREN: Comparator 1 Voltage Reference Enable bit circuit powered on and routed to C1V REF 0 = 1.2 Volt VR routed to C1V ...
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... REF output on RA1/AN1/C12IN0-/V REF bit 0 Unimplemented: Read as ‘0’ Note 1: Buffer amplifier common mode limitations require V 2: VREN is fixed high for PIC16HV785 device. © 2008 Microchip Technology Inc. PIC16F785/HV785 REF R/W-0 R/W-0 R/W-0 VRBB VREN VROE U = Unimplemented bit, read as ‘0’ ...
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... PIC16F785/HV785 10.2.1 VR STABILIZATION PERIOD When the Voltage Reference module is enabled, it will require some time for the reference and its amplifier circuits to stabilize. The user program must include a small delay routine to allow the module to settle. See Section 19.0 “Electrical Specifications” for the minimum delay requirement ...
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... RC6/AN8/OP1- RC3/AN7/C12IN3-/OP1 RB5/AN11/OP2+ RB4/AN10/OP2- RC2/AN6/C12IN2-/OP2 © 2008 Microchip Technology Inc. PIC16F785/HV785 11.2 OPAxCON Register The OPA module is enabled by setting the OPAON bit of the OPAxCON Register. When enabled, OPAON forces the output driver of RC3/AN7/C12IN3-/OP1 for OPA1, and RC2/AN6/C12IN2-/OP2 for OPA2, into tristate to prevent contention between the driver and the OPA output ...
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... PIC16F785/HV785 REGISTER 11-1: OPA1CON: OP AMP 1 CONTROL REGISTER R/W-0 U-0 U-0 OPAON — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OPAON: Op Amp Enable bit Amp 1 is enabled Amp 1 is disabled bit 6-0 Unimplemented: Read as ‘0’ ...
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... Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used for the OPA module. © 2008 Microchip Technology Inc. PIC16F785/HV785 Leakage current is a measure of the small source or sink currents on the OPA+ and OPA- inputs. To mini- mize the effect of leakage currents, the effective imped- ances connected to the OPA+ and OPA- inputs should be kept as small as possible and equal ...
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... PIC16F785/HV785 NOTES: DS41249E-page 78 © 2008 Microchip Technology Inc. ...
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... CONVERTER (A/D) MODULE The analog-to-digital converter (A/D) allows conversion of an analog input signal to a 10-bit binary representa- tion of that signal. The PIC16F785/HV785 has twelve analog I/O inputs, plus two internal inputs, multiplexed into one sample and hold circuit. The output of the sam- ple and hold is connected to the input of the converter ...
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... Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. 12.1.2 CHANNEL SELECTION There are fourteen analog channels on the PIC16F785/ HV785. The CHS<3:0> bits of the ADCON0 Register control which channel is connected to the sample and hold circuit. TABLE 12- ...
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... MSB bit 7 (ADFM = 1) bit 7 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. PIC16F785/HV785 If the conversion must be aborted, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers will not be updated with the partially complete A/D conversion ADRESH:ADRESL registers will retain the value of the previous conversion ...
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... PIC16F785/HV785 REGISTER 12-1: ANSEL0: ANALOG SELECT REGISTER R/W-1 R/W-1 R/W-1 ANS7 ANS6 ANS5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ANS<7:0>: Analog Select bits Analog select between analog or digital function on pins AN<7:0>, respectively Analog input. Pin is assigned as analog input. ...
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... This bit is automatically cleared by hardware when the A/D conversion has completed A/D conversion completed/not in progress bit 0 ADON: A/D Enable bit 1 = A/D converter module is enabled 0 = A/D converter is shut-off and consumes no operating current © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 CHS2 CHS1 CHS0 U = Unimplemented bit, read as ‘ ...
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... PIC16F785/HV785 REGISTER 12-4: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 — ADCS2 ADCS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits 000 = F /2 OSC ...
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... The A/D conversion time per bit is defined minimum wait required before the next acquisition starts. © 2008 Microchip Technology Inc. PIC16F785/HV785 EXAMPLE 12-1: ;This code block configures the A/D ;for polling, Vdd reference, R/C clock ;and RA0 input. ; ;Conversion start and wait for complete ...
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... PIC16F785/HV785 12.2 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in Figure 12-4. The source impedance (R ) and the internal sampling ...
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... S C PIN Legend Input Capacitance PIN V = Threshold Voltage Leakage current at the pin due to various junctions LEAKAGE R = Interconnect Resistance Sampling Switch C = Sample/Hold Capacitance (from DAC) HOLD © 2008 Microchip Technology Inc. PIC16F785/HV785 V DD Sampling Switch V = 0.6V T ≤ LEAKAGE V = 0.6V T ± 500 HOLD ...
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... PIC16F785/HV785 12.3 A/D Operation During Sleep The A/D Converter module can operate during Sleep. This requires the A/D clock source to be set to the F option. When the RC clock source is selected, the A/D waits one instruction before starting the conversion. This allows the SLEEP instruction to be executed, thus eliminating much of the switching noise from the con- version ...
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... Legend unknown unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for A/D module. © 2008 Microchip Technology Inc. PIC16F785/HV785 The appropriate analog input channel must be selected and the minimum acquisition done before the “special event trigger” sets the GO/DONE bit (starts a conversion) ...
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... PIC16F785/HV785 NOTES: DS41249E-page 90 © 2008 Microchip Technology Inc. ...
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... Phase granularity is a function of the period count value. For example, if PER<4:0> each output can be shifted in 90° steps (see Equation 13-2). © 2008 Microchip Technology Inc. PIC16F785/HV785 EQUATION 13-2: Phase 13.3 PWM Duty Cycle Each PWM output is driven inactive, terminating the drive period, by asynchronous feedback through the internal comparators ...
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... PIC16F785/HV785 13.5 Active PWM Output Level The PWM output signal can be made active-high or active-low by setting or resetting the corresponding POL bit (see Register 13-3 and Register 13-4). When POL is ‘1’ the active output state ‘0’ the active output state 13.6 ...
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... The PH1 pin is driven by the PWM signal 0 = The PH1 pin is not used for PWM functions Note 1: Blanking is disabled when operating in complementary mode. See COMOD<1:0> bits in the PWMCON1 register (Register 13-5) for more information. © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 BLANK1 ...
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... PIC16F785/HV785 REGISTER 13-2: PWMCLK: PWM CLOCK CONTROL REGISTER R/W-0 R/W-0 R/W-0 PWMASE PWMP1 PWMP0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 PWMASE: PWM Auto-Shutdown Event Status bit 0 = PWM outputs are operating shutdown event has occured. PWM outputs are inactive. ...
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... Complementary drive start is delayed by 1 pwm_clk pulse ••••• = • • • 11111 = Complementary drive start is delayed by 31 pwm_clk pulses Note 1: See PWMCON1 register (Register 13-5). © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 R/W-0 PH4 PH3 PH2 U = Unimplemented bit, read as ‘ ...
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... PIC16F785/HV785 REGISTER 13-4: PWMPH2: PWM PHASE 2 CONTROL REGISTER R/W-0 R/W-0 R/W-0 POL C2EN C1EN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 POL: PH2 Output Polarity bit 1 = PH2 Pin is active low 0 = PH2 Pin is active high bit 6 C2EN: Comparator 2 Enable bit When COMOD< ...
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... SYNC Phase1 setup: PH<4:0> = 0x00, C1EN = 1, BLANK1 = 0 pha1 SHUTDOWN pwm_clk 2 pwm_count 0 1 Phase2 setup: PH<4:0> = 0x02, C2EN = 1, BLANK2 = 1 pha2 FIGURE 13-3: TWO-PHASE PWM START-UP TIMING F OSC PWMP<1:0> 01, PER<4:0> pwm_clk pwm_count SYNC PHnEN pwm_clk pwm_count PHnEN © 2008 Microchip Technology Inc. PIC16F785/HV785 ...
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... Comparator 1 will rise, resulting in a higher threshold voltage and, conse- quently, longer PWM drive pulses into Q1. If the output voltage is too high, then the voltage to the non-inverting input of Comparator 1 will fall, resulting in shorter PWM drive pulses into Q1. PIC16F785 F OSC FET Driver PH1 ...
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... B'10101100' ;C1V MOVWF VRCON ;see data sheet page 72 ;Everything is setup at this point so now it is time to enable PH1 BANKSEL PWMCON0 BSF PWMCON0,PH1EN ;enable PH1 ;Module is running autonomously at this point © 2008 Microchip Technology Inc. PIC16F785/HV785 on, low range REN REF DD , -:AN6 REF DS41249E-page 99 ...
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... PIC16F785/HV785 13.9 Complementary Output Mode The Two-Phase PWM module may be configured to operate in a Complementary Output mode where PH1 and PH2 are always 180 degrees out-of-phase (see Figure 13-5). Three complementary available and are selected by the COMOD<1:0> bits in the PWMCON1 register (see Register 13-5). The differ- ...
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... PS<1:0> F OSC Prescale 5 PWMPH1<4:0> 5 PWMPH2<4:0> PWMPH1<C1EN> C1OUT PWMPH1<C2EN> C2OUT COMOD<1:0> Note 1: Reset dominant. © 2008 Microchip Technology Inc. PIC16F785/HV785 R/W-0 R/W-0 CMDLY4 CMDLY3 CMDLY2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) PH1EN pwm_reset PH2EN PWMASE Shutdown PASEN pwm_clk Phase ...
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... PIC16F785/HV785 FIGURE 13-6: COMPLEMENTARY OUTPUT PWM TIMING F OSC PWMP<1:0> 01, PER<4:0> pwm_clk 3 pwm_count 0 1 SYNC C1OUT Phase 1 setup: PH<4:0> = 0x00, C1EN = 1, BLANKx = X, COMOD<1:0> = 0x01 pha1 pha2 Delay Shutdown TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH PWM Name Bit 7 Bit 6 Bit 5 CM1CON0 C1ON C1OUT C1OE ...
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... EEDAT • EEADR EEDAT holds the 8-bit data for read/write, and EEADR holds the address of the EEPROM location being accessed. The PIC16F785/HV785 has 256 bytes of data EEPROM with an address range from 0h to FFh. REGISTER 14-1: EEDAT: EEPROM DATA REGISTER R/W-0 ...
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... PIC16F785/HV785 14.1 EECON1 and EECON2 Registers EECON1 is the control register with four low-order bits physically implemented. The upper four bits are non- implemented and read as ‘0’s. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software ...
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... EEPROM. The WREN bit is not cleared by hardware. © 2008 Microchip Technology Inc. PIC16F785/HV785 After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. ...
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... PIC16F785/HV785 14.6 Data EEPROM Operation During Code-Protect Data memory can be code-protected by programming the CPD bit in the Configuration Word (Register 15.2) to ‘0’. When the data memory is code-protected, the CPU is able to read and write data to the data EEPROM recommended that the user code protect the program memory when code protecting the data memory ...
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... SPECIAL FEATURES OF THE CPU The PIC16F785/HV785 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power sav- ing features and offer code protection. These features are: • Reset: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) • ...
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... PIC16F785/HV785 REGISTER 15-1: CONFIG: CONFIGURATION WORD U-0 U-0 U-0 — — — bit 15 R/P-0 R/P-1 R/P-1 CPD CP MCLRE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 13-12 FCMEN: Fail-Safe Clock Monitor Enabled bit 1 = Fail-Safe Clock Monitor is enabled ...
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... Reset The PIC16F785/HV785 differentiates between various kinds of Reset: • Power-on Reset (POR) • WDT Reset during normal operation • WDT Reset during Sleep • MCLR Reset during normal operation • MCLR Reset during Sleep • Brown-out Reset (BOR) Some registers are not affected in any Reset condition; ...
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... For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). 15.2.2 MASTER CLEAR (MCLR) PIC16F785/HV785 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. ...
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... BOR CALIBRATION The PIC16F785/HV785 stores the BOR calibration values in fuses located in the Calibration Word (2008h). The Calibration Word is not erased when using the specified bulk erase sequence in the “PIC16F785/ HV785 Memory Programming (DS41237) and thus, does not require reprogramming. Note: Address 2008h is beyond the user program memory space ...
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... Then bringing MCLR high will begin execution immediately (see Figure 15-6). This is useful for testing purposes or to synchronize more than one PIC16F785/HV785 device operating in parallel. Table 15-5 shows the Reset conditions for some special registers, while Table 15-4 shows the Reset conditions for all the registers ...
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... V DD MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 15-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset © 2008 Microchip Technology Inc. PIC16F785/HV785 T PWRT T OST T PWRT T OST ) DD T PWRT T OST DS41249E-page 113 ...
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... PIC16F785/HV785 TABLE 15-4: INITIALIZATION CONDITION FOR REGISTERS Register Address Power-on Reset W — xxxx xxxx INDF 00h/80h xxxx xxxx TMR0 01h xxxx xxxx PCL 02h/82h 0000 0000 STATUS 03h/83h 0001 1xxx FSR 04h/84h xxxx xxxx PORTA 05h --x0 x000 PORTB 06h xx00 ---- ...
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... If Reset was due to brown-out, then bit All other Resets will cause bit Analog channels read 0 but data latches are unknown. 7: Analog channels read 0 but data latches are unchanged. © 2008 Microchip Technology Inc. PIC16F785/HV785 Wake-up from Sleep through interrupt MCLR Reset Wake-up from Sleep through WDT Time-out WDT Reset (1) ...
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... PIC16F785/HV785 TABLE 15-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from Sleep Legend unchanged unknown, – = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the interrupt vector (0004h) after execution ...
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... Interrupts The PIC16F785/HV785 has 11 sources of interrupt: • External Interrupt RA2/INT • TMR0 Overflow Interrupt • PORTA Change Interrupt • 2 Comparator Interrupts • A/D Interrupt • Timer1 Overflow Interrupt • Timer2 Match Interrupt • EEPROM Data Write Interrupt • Fail-Safe Clock Monitor Interrupt • ...
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... PIC16F785/HV785 15.3.1 RA2/AN2/T0CKI/INT/C1OUT INTERRUPT External interrupt on RA2/AN2/T0CKI/INT/C1OUT pin is edge-triggered; either rising, if INTEDG bit of the OPTION Register is set, or falling, if INTEDG bit is clear. When a valid edge appears on the RA2/AN2/ T0CKI/INT/C1OUT pin, the INTF bit of the INTCON Register is set. This interrupt can be disabled by clear- ing the INTE control bit of the INTCON Register ...
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... GIE PEIE T0IE PIE1 EEIE ADIE CCP1IE PIR1 EEIF ADIF CCP1IF Legend unknown unchanged, – = unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by the Interrupt module. © 2008 Microchip Technology Inc. PIC16F785/HV785 (1) (2) Interrupt Latency Inst ( — ...
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... W and STATUS registers). This must be implemented in software. Since the last 16 bytes of all banks are common in the PIC16F785/HV785 (see Figure 2-2), temporary hold- ing registers W_TEMP and STATUS_TEMP should be placed in here. These 16 locations do not require banking, therefore, making it easier to save and restore context ...
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... Watchdog Timer (WDT) For PIC16F785/HV785, the WDT has been modified from previous PIC16FXXX devices. The new WDT is code and functionally compatible with previous PIC16FXXX WDT modules and adds a 16-bit prescaler to the WDT. This allows the user to scale the value for the WDT and TMR0 at the same time ...
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... PIC16F785/HV785 REGISTER 15-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Period Select bits Bit Value = Prescale Rate ...
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... External Interrupt from INT pin Other peripherals cannot generate interrupts since, during Sleep, no on-chip clocks are present. © 2008 Microchip Technology Inc. PIC16F785/HV785 When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit (and PEIE bit where applicable) must be set (enabled) ...
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... Program/Verify. Only the Least Significant 7 bits of the ID locations are used. 15.9 In-Circuit Serial Programming™ (ICSP™) The PIC16F785/HV785 microcontrollers can be seri- ally programmed while in the end application circuit. This is simply done with five lines: • Clock • Data • ...
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... ICD 2 connector. On the bottom of the header is a 20-pin socket that plugs into the user’s target via the 20-pin stand-off connector. • When the ICD pin on the PIC16F785-ICD device is held low, the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB ICD 2 ...
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... PIC16F785/HV785 16.0 VOLTAGE REGULATOR The PIC16HV785 includes a permanent internal 5 volt (nominal) shunt regulator in parallel with the V This eliminates the need for an external voltage regula- tor in systems sourced by an unregulated supply. All external devices connected directly to the V share the regulated supply voltage and contribute to ...
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... INSTRUCTION SET SUMMARY The PIC16F785/HV785 instruction set is highly orthog- onal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction ...
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... PIC16F785/HV785 TABLE 17-2: PIC16F785/HV785 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS f, d Add W and f ADDWF f, d AND W with f ANDWF f Clear f CLRF – Clear W CLRW f, d Complement f COMF f, d Decrement f DECF f, d Decrement f, Skip if 0 DECFSZ f, d Increment f INCF f, d Increment f, Skip if 0 ...
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... Operation: Status Affected: Z Description: The contents of W register are AND’ed with the eight-bit literal ‘k’. The result is placed in the W register. © 2008 Microchip Technology Inc. PIC16F785/HV785 ANDWF AND W with f Syntax: [label] ANDWF f,d 0 ≤ f ≤ 127 Operands: d ∈ [0,1] (W) .AND. (f) → ...
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... PIC16F785/HV785 BTFSC Bit Test f, Skip if Clear Syntax: [label] BTFSC f,b 0 ≤ f ≤ 127 Operands: 0 ≤ b ≤ 7 Operation: skip if (f<b> Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the ...
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... If the result is ‘1’, the next instruc- tion is executed. If the result is ‘0’, then a NOP is executed instead, making it a two-cycle instruction. © 2008 Microchip Technology Inc. PIC16F785/HV785 GOTO Unconditional Branch Syntax: [ label ] GOTO k 0 ≤ k ≤ 2047 Operands: k → ...
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... PIC16F785/HV785 IORLW Inclusive OR Literal with W Syntax: [ label ] IORLW k 0 ≤ k ≤ 255 Operands: (W) .OR. k → (W) Operation: Status Affected: Z Description: The contents of the W register are OR’ed with the eight-bit literal ‘k’. The result is placed in the W register. IORWF Inclusive OR W with f Syntax: ...
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... Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. © 2008 Microchip Technology Inc. PIC16F785/HV785 RLF Syntax: Operands: Operation: Status Affected: Encoding: 0000 1001 Description: ...
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... PIC16F785/HV785 SUBLW Subtract W from Literal Syntax: [label] SUBLW k 0 ≤ k ≤ 255 Operands (W) → (W) Operation: Status C, DC, Z Affected: Encoding: 11 110x kkkk Description: The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register result is positive or zero ...
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... Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’ the result is stored back in register ‘f’. © 2008 Microchip Technology Inc. PIC16F785/HV785 f,d dfff ffff DS41249E-page 135 ...
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... PIC16F785/HV785 NOTES: DS41249E-page 136 © 2008 Microchip Technology Inc. ...
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... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2008 Microchip Technology Inc. PIC16F785/HV785 18.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
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... PIC16F785/HV785 18.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
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... Microchip Technology Inc. PIC16F785/HV785 18.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, connecting to the host PC via an RS-232 or high-speed USB interface ...
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... PIC16F785/HV785 18.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins. ...
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... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: Voltage spikes below V SS Thus, a series resistor of 50-100 pulling this pin directly to V © 2008 Microchip Technology Inc. PIC16F785/HV785 ................................................................................. -0. )...................................................................................................................... ± )................................................................................................................ ± – ∑ I ...
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... PIC16F785/HV785 FIGURE 19-1: PIC16F785/HV785 WITH ANALOG DISABLED VOLTAGE-FREQUENCY GRAPH, ≤ ≤ -40°C T +125°C A 5.5 5.0 4.5 4 (Volts) 3.5 3.0 2.5 2 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Frequency denotes system clock frequency. When using the HFINTOSC the system clock is after the postscaler ...
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... T Min Typ† Max Units F OSC 2.0 — 5.5 V PIC16F785 with A/D off 2.2 — 5.5 V PIC16F785 with A/D on, 0°C to +125°C 2.5 — 5.5 V PIC16F785 with A/D on, -40°C to +125°C 4 MHz ≤ F 3.0 — 5 MHz ≤ F 4.5 — ...
Page 146
... PIC16F785/HV785 19.2 DC Characteristics: PIC16F785/HV785-I (Industrial) DC CHARACTERISTICS Param Device Characteristics No. D010 Supply Current ( D011 D012 D013 D014 D015 D016 D017 D018 † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ...
Page 147
... DC Characteristics: PIC16F785/HV785-I (Industrial) DC CHARACTERISTICS Param Device Characteristics No. D020 Power-down Base Current ( D021 D022 D023 D023A D024 D024A D025 D026 D027 D028 † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 148
... PIC16F785/HV785 19.3 DC Characteristics: PIC16F785/HV785-E (Extended) DC CHARACTERISTICS Param Device Characteristics No. D010E Supply Current ( D011E D012E D013E D014E D015E D016E D017E D018E † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. ...
Page 149
... DC Characteristics: PIC16F785/HV785-E (Extended) DC CHARACTERISTICS Param Device Characteristics No. D020E Power-down Base Current ( D021E D022E D023E D023E D024E D024E D025E D026E D027E D028E † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested ...
Page 150
... PIC16F785/HV785 19.4 DC Characteristics: PIC16F785/HV785-I (Industrial), PIC16F785/HV785-E (Extended) DC CHARACTERISTICS Param Sym Characteristic No. V Input Low Voltage IL I/O ports D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (RC mode) D033 OSC1 (XT and LP modes) D033A OSC1 (HS mode) V Input High Voltage ...
Page 151
... DC Characteristics: PIC16F785/HV785-I (Industrial), PIC16F785/HV785-E (Extended) (Continued) DC CHARACTERISTICS Param Sym Characteristic No. Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin D101 C All I/O pins IO Data EEPROM Memory D120 E Byte Endurance D D120A E Byte Endurance D D121 V V for Read/Write DRW DD D122 T Erase/Write cycle time ...
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... PIC16F785/HV785 19.5 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings Fall ...
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... All devices are tested to operate at ‘min’ values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock) for all devices. © 2008 Microchip Technology Inc. PIC16F785/HV785 ...
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... PIC16F785/HV785 FIGURE 19-4: CLKOUT AND I/O TIMING Q4 OSC1 CLKOUT I/O pin (Input) I/O pin Old Value (Output) TABLE 19-2: CLKOUT AND I/O TIMING REQUIREMENTS Param Sym Characteristic No OSC1↑ to CLKOUT↓ OSC1↑ to CLKOUT↑ CLKOUT rise time CLKOUT fall time ...
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... POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins © 2008 Microchip Technology Inc. PIC16F785/HV785 Freq. Min Typ† Max Tolerance ±1% 7.92 8.00 8.08 (1) ±2% 7.84 8.00 8.16 ±5% 7.60 8.00 8.40 — ...
Page 156
... PIC16F785/HV785 FIGURE 19-6: BROWN-OUT RESET TIMING AND CHARACTERISTICS BOR (Device in Brown-out Reset) Reset (due to BOR) Note delay only if PWRTE bit in Configuration Word is programmed to ‘0’. TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param Sym Characteristic No ...
Page 157
... Delay from external clock edge to timer increment TMR * These parameters are characterized but not tested. † Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. PIC16F785/HV785 Characteristic ...
Page 158
... PIC16F785/HV785 FIGURE 19-8: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCP1 (Capture mode) CCP1 (Compare or PWM mode) Note: Refer to Figure 19-2 for load conditions. TABLE 19-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Param Symbol Characteristic No. 50 CCP1 input low time CC 51 CCP1 input high time CC 52 CCP1 input period ...
Page 159
... Voltage Reference Output Buffer Specifications Param Symbol Characteristics No. VB01* CL External capacitor load * These parameters are characterized but not tested. © 2008 Microchip Technology Inc. PIC16F785/HV785 Standard Operating Conditions (unless otherwise stated) -40°C ≤ T Operating temperature Min Typ Max Units ±5 ±10 — 0 — ...
Page 160
... PIC16F785/HV785 TABLE 19-11: OPERATIONAL AMPLIFIER (OPA) MODULE DC SPECIFICATIONS OPA DC CHARACTERISTICS Param Sym Characteristics No. OPA01 V Input Offset Voltage OS Input current and impedance OPA02* I Input bias current B OPA03* I Input offset bias current OS Common Mode OPA04* V Common mode input range CM OPA05* CMR Common mode rejection ...
Page 161
... Shunt Current SHUNT SR03* T Settling Time SETTLE SR04* C Load Capacitance LOAD ΔI SR05* Regulator operating current SNT * These parameters are characterized but not tested. TABLE 19-15: PIC16F785/HV785 A/D CONVERTER CHARACTERISTICS: Param Sym Characteristic No. A01 N Resolution R A03 E Integral Error IL A04 E Differential Error ...
Page 162
... OSC Q4 A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 19-16: PIC16F785/HV785 A/D CONVERSION REQUIREMENTS Param Sym Characteristic No. 130 T A/D Clock Period AD 130 T A/D Internal RC AD Oscillator Period ...
Page 163
... A/D CLK A/D DATA ADRES ADIF GO 132 SAMPLE Note 1: If the A/D clock source is selected as RC, a time of T allows the SLEEP instruction to be executed. TABLE 19-17: PIC16F785/HV785 A/D CONVERSION REQUIREMENTS (SLEEP MODE) Param Sym Characteristic No. 130 T A/D Internal RC AD Oscillator Period ...
Page 164
... PIC16F785/HV785 NOTES: DS41249E-page 162 © 2008 Microchip Technology Inc. ...
Page 165
... Typical: Statistical Mean @25°C 3.0 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 2.5 2.0 1.5 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz © 2008 Microchip Technology Inc. PIC16F785/HV785 vs. F OVER V (EC MODE) OSC DD 6 MHz 8 MHz 10 MHz 12 MHz 14 MHz F OSC DD 5.5V 5 ...
Page 166
... PIC16F785/HV785 FIGURE 20-2: MAXIMUM I DD 4.0 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 3.5 (-40°C to 125°C) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1 MHz 2 MHz 4 MHz FIGURE 20-3: TYPICAL I DD 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-case Temp) + 3σ ...
Page 167
... Typical: Statistical Mean @25°C 800 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 700 600 500 400 300 200 100 0 2.0 2.5 © 2008 Microchip Technology Inc. PIC16F785/HV785 vs. F OVER V (HS MODE) OSC DD HS Mode 4.0V 3.5V 3.0V 10 MHz 16 MHz F OSC vs. V ...
Page 168
... PIC16F785/HV785 FIGURE 20-6: MAXIMUM I DD 1,400 Typical: Statistical Mean @25°C 1,200 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 1,000 800 600 400 200 0 2.0 2.5 FIGURE 20-7: I vs. V (LP MODE Typical Typical Typical: Statistical Mean @25°C Typical: Statistical Mean @25× ...
Page 169
... MAXIMUM I DD 1,400 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 1,200 (-40°C to 125°C) 1,000 800 600 400 200 0 2.0 2.5 © 2008 Microchip Technology Inc. PIC16F785/HV785 vs. V OVER F (EXTRC MODE) DD OSC 4 MHz 1 MHz 3.0 3.5 4.0 V (V) DD vs. V OVER F ...
Page 170
... PIC16F785/HV785 FIGURE 20-10: I vs. V OVER Typical: Statistical Mean @25°C 70 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125° 2.0 2.5 FIGURE 20-11: TYPICAL I DD 1,600 Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 1,400 (-40°C to 125°C) 1,200 1,000 800 600 ...
Page 171
... Microchip Technology Inc. PIC16F785/HV785 vs. F OVER V (HFINTOSC MODE) OSC DD 500 kHz 1 MHz 2 MHz F OSC vs. V (SLEEP MODE, ALL PERIPHERALS DISABLED (Sleep Mode all Periphreals Disabled) Max 85×C Max 125× ...
Page 172
... PIC16F785/HV785 FIGURE 20-14: MAXIMUM I PD 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 2.0 2.5 FIGURE 20-15: COMPARATOR I ( 200 180 160 140 120 100 80 60 Typical: Statistical Mean @25°C 40 Maximum: Mean (Worst-case Temp) + 3σ 20 (-40°C to 125°C) 0 2.0 2.5 DS41249E-page 170 vs ...
Page 173
... BOR I vs 160 Typical: Statistical Mean @25°C 140 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 120 100 2.5 3.0 © 2008 Microchip Technology Inc. PIC16F785/HV785 vs. V (BOTH COMPARATORS ENABLED) CXSP Max Typical 3.5 4.0 4.5 V (V) DD OVER TEMPERATURE DD Maximum Typical 3.5 4 ...
Page 174
... PIC16F785/HV785 FIGURE 20-18: TYPICAL WDT I 3.5 Typical: Statistical Mean @25°C 3.0 Maximum: Mean (Worst-case Temp) + 3σ Typical Max 85×C Max 125×C (-40°C to 125°C) 2 1.700 3.000 2.51.850 3.500 2.5 3 2.000 4.000 3.52.250 4.750 4 2.500 5.500 2.0 4.52.750 6.250 5 3.000 7.000 5 ...
Page 175
... Typical: Statistical Mean @25°C 160 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 140 120 100 2.0 2.5 © 2008 Microchip Technology Inc. PIC16F785/HV785 OVER TEMPERATURE (HIGH RANGE) DD High Range Max. 125°C Max. 85°C Typical 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE (LOW RANGE) DD Max. 125° ...
Page 176
... PIC16F785/HV785 FIGURE 20-22: T1OSC I vs 60.0 Typical: Statistical Mean @25°C 50.0 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 40.0 30.0 Typ 25×C Max 85×C 20.0 2 2.500 2.5 2.850 3 3.200 3.5 3.600 10.0 4 4.000 4.5 4.400 5 4.800 0.0 5.5 5.200 2.0 2 ...
Page 177
... Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ 1.0 (-40°C to 125°C) 0.5 0.0 0.0 -0.5 -1.0 © 2008 Microchip Technology Inc. PIC16F785/HV785 = 5.0V) DD Max. 125°C Max. 85°C Typ. 25°C Min. -40°C 6.5 7.0 7.5 8.0 8.5 ...
Page 178
... PIC16F785/HV785 FIGURE 20-26: V vs. I OVER TEMPERATURE ( 5.5 5.0 4.5 4.0 Typical: Statistical Mean @25°C 3.5 Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.0 0.0 -0.5 -1.0 FIGURE 20-27: TTL INPUT THRESHOLD V 1.7 Typical: Statistical Mean @25°C 1.5 Maximum: Mean (Worst-case Temp) + 3σ ...
Page 179
... FIGURE 20-29: LFINTOSC FREQUENCY vs. V 45,000 40,000 35,000 30,000 25,000 20,000 15,000 10,000 5,000 0 2.0 2.5 © 2008 Microchip Technology Inc. PIC16F785/HV785 vs (ST Input, -40×C TO 125×C) 3.0 3.5 4.0 V (V) DD OVER TEMPERATURE (31 kHz) DD LFINTOSC 31Khz Max. -40°C Typ. 25°C Min. 85°C Min. 125° ...
Page 180
... PIC16F785/HV785 FIGURE 20-30: ADC CLOCK PERIOD vs 125°C 6 85°C 25°C 4 -40° 2.0 2.5 FIGURE 20-31: TYPICAL HFINTOSC START-UP TIMES vs 85°C 12 25°C 10 -40° 2.0 2.5 3.0 DS41249E-page 178 OVER TEMPERATURE DD Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ ...
Page 181
... Microchip Technology Inc. PIC16F785/HV785 OVER TEMPERATURE DD -40C to +85C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ (-40°C to 125°C) 3.5 4.0 4.5 V (V) DD OVER TEMPERATURE DD -40C to +85C Typical: Statistical Mean @25°C Maximum: Mean (Worst-case Temp) + 3σ ...
Page 182
... PIC16F785/HV785 FIGURE 20-34: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 FIGURE 20-35: TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE 2.0 2.5 DS41249E-page 180 3.0 3.5 4.0 4.5 V (V) DD 3.0 3.5 4.0 V (V) DD (25°C) DD 5.0 5.5 (85°C) DD 4.5 5.0 5.5 © 2008 Microchip Technology Inc. ...
Page 183
... FIGURE 20-36: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 FIGURE 20-37: TYPICAL HFINTOSC FREQUENCY CHANGE vs 2.0 2.5 © 2008 Microchip Technology Inc. PIC16F785/HV785 3.0 3.5 4.0 4.5 V (V) DD 3.0 3.5 4.0 4.5 V (V) DD (125°C) DD 5.0 5.5 (-40°C) DD 5.0 5.5 DS41249E-page 181 ...
Page 184
... PIC16F785/HV785 FIGURE 20-38: TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (3V) Typical VP6 Reference Voltage vs. Temperature (VDD=3V) 0.66 0.64 0.62 0.6 0.58 0.56 0.54 0.52 -40°C FIGURE 20-39: TYPICAL VP6 REFERENCE VOLTAGE OVER TEMPERATURE (5V) Typical VP6 Reference Voltage vs. Temperature (VDD=5V) 0.66 0.64 0.62 ...
Page 185
... FIGURE 20-40: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 25°C) 100 FIGURE 20-41: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 85°C) Typical VP6 Reference Voltage Distribution (VDD=3V, 85× © 2008 Microchip Technology Inc. PIC16F785/HV785 Parts = 150 Voltage (V) Parts = 150 Voltage (V) DS41249E-page 183 ...
Page 186
... PIC16F785/HV785 FIGURE 20-42: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, 125° FIGURE 20-43: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (5V, -40° DS41249E-page 184 Parts = 150 Voltage (V) Parts = 150 Voltage (V) © 2008 Microchip Technology Inc. ...
Page 187
... TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 25°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 25× FIGURE 20-45: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 85°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 85× © 2008 Microchip Technology Inc. PIC16F785/HV785 Parts = 150 Voltage (V) Parts = 150 Voltage (V) DS41249E-page 185 ...
Page 188
... PIC16F785/HV785 FIGURE 20-46: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, 125°C) Typical VP6 Reference Voltage Distribution (VDD=5V, 25× FIGURE 20-47: TYPICAL VP6 REFERENCE VOLTAGE DISTRIBUTION (3V, -40° DS41249E-page 186 Parts = 150 Voltage (V) Voltage (V) © 2008 Microchip Technology Inc. Parts = 150 ...
Page 189
... For PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2008 Microchip Technology Inc. PIC16F785/HV785 Example PIC16F785-I/P 0810017 Example PIC16F785 -E/SO 0810017 Example PIC16F785 -I/SS 0810017 Example 16F785 -I/ML 0810017 DS41249E-page 187 ...
Page 190
... PIC16F785/HV785 N NOTE DS41249E-page 188 © 2008 Microchip Technology Inc. ...
Page 191
... N NOTE © 2008 Microchip Technology Inc. PIC16F785/HV785 α h φ β DS41249E-page 189 ...
Page 192
... PIC16F785/HV785 D N NOTE DS41249E-page 190 © 2008 Microchip Technology Inc. φ L ...
Page 193
... D TOP VIEW A3 © 2008 Microchip Technology Inc. PIC16F785/HV785 EXPOSED PAD NOTE 1 BOTTOM VIEW DS41249E-page 191 ...
Page 194
... PIC16F785/HV785 DS41249E-page 192 © 2008 Microchip Technology Inc. ...
Page 195
... Microchip Technology Inc. PIC16F785/HV785 APPENDIX B: MIGRATING FROM OTHER PIC DEVICES This discusses some of the issues in migrating from the ® PIC16F684 PIC device to the PIC16F785/HV785. B.1 PIC16F684 to PIC16F785/HV785 TABLE B-1: FEATURE COMPARISON Feature PIC16F684 Max Operating 20 MHz Speed Max Program ...
Page 196
... PIC16F785/HV785 NOTES: DS41249E-page 194 © 2008 Microchip Technology Inc. ...
Page 197
... Comparator 2 .............................................................. 66 Compare ..................................................................... 58 CVref........................................................................... 71 Fail-Safe Clock Monitor (FSCM) ................................. 31 In-Circuit Serial Programming Connections.............. 125 Interrupt Logic ........................................................... 118 On-Chip Reset Circuit ............................................... 109 OPA Module................................................................ 75 PIC16F785/HV785........................................................ 5 RA0 Pin....................................................................... 38 RA1 Pin....................................................................... 38 RA2 Pin....................................................................... 39 RA3 Pin....................................................................... 39 RA4 Pin....................................................................... 40 RA5 Pin....................................................................... 40 RB4 and RB5 Pins ...................................................... 43 RB6 Pin....................................................................... 43 RB7 Pin ...
Page 198
... PIC16F785/HV785 Interrupt Context Saving ........................................... 120 Code Protection ................................................................ 124 Comparator Module ............................................................ 63 Associated Registers .................................................. 74 C1 Output State Versus Input Conditions ................... 63 C2 Output State Versus Input Conditions ................... 66 Comparator Interrupts ................................................. 69 Effects of Reset........................................................... 69 Comparator Voltage Reference (CV ) REF Specifications ............................................................ 157 Comparators C2OUT as T1 Gate ..................................................... 52 Specifications ............................................................ 157 Compare Module. See Capture/Compare/PWM (CCP) CONFIG Register ...
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... Specifications............................................................ 152 PORTB................................................................................ 42 Associated Registers .................................................. 44 Pin Descriptions and Diagrams................................... 43 RB4 ............................................................................. 43 RB5 ............................................................................. 43 RB6 ............................................................................. 43 RB7 ............................................................................. 43 PORTC ............................................................................... 45 Associated Registers ............................................ 34, 48 © 2008 Microchip Technology Inc. PIC16F785/HV785 Pin Descriptions and Diagrams .................................. 46 RC0 ............................................................................ 46 RC1 ............................................................................ 46 RC2 ............................................................................ 47 RC3 ............................................................................ 47 RC4 ............................................................................ 47 RC5 ............................................................................ 48 RC6 ............................................................................ 46 RC7 ............................................................................ 46 Specifications ........................................................... 152 Power-Down Mode (Sleep)............................................... 123 Power-up Timer (PWRT) ...
Page 200
... PIC16F785/HV785 PIR1 (Peripheral Interrupt Register 1) ........................ 19 PORTA........................................................................ 35 PORTB........................................................................ 42 PORTC ....................................................................... 45 PWMCLK (PWM Clock Control) ................................. 94 PWMCON0 (PWM Control 0) ..................................... 93 PWMCON1 (PWM Control 1) ................................... 101 PWMPH1 (PWM Phase 1 control) .............................. 95 PWMPH2 (PWM Phase 2 control) .............................. 96 REFCON (VR Control) ................................................ 73 Reset Values............................................................. 114 Reset Values (Special Registers) ............................. 116 Special Function Registers ........................................... 9 Special Register Summary ...