PIC16F785-I/SO Microchip Technology, PIC16F785-I/SO Datasheet - Page 112

• Manufacturer Part Number: PIC16F785-I/SO
• Description: IC PIC MCU FLASH 2KX14 20SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F785-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 20-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 17
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOICXLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC162060 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F785/HV785
15.2.1
The on-chip POR circuit holds the chip in Reset until
V
operation. A minimum rise rate for V
Section 19.0 “Electrical Specifications” for details. If
the BOR is enabled, the minimum rise rate specifica-
tion does not apply. The BOR circuitry will keep the
device in Reset until V
Section 15.2.4 “Brown-Out Reset (BOR)”)
The POR circuit, on this device, has a POR re-arm cir-
cuit. This circuit is designed to ensure a re-arm of the
POR circuit if V
age (V
Once V
required time, the POR Reset will reactivate and
remain in Reset until V
than V
tiated to allow V
safely above V
When the device starts normal operation (exits the
Reset condition), device operating parameters
(i.e., voltage, frequency, temperature, etc.) must be
met to ensure operation. If these conditions are not
met, the device must be held in Reset until the
operating conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
15.2.2
PIC16F785/HV785 has a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from earlier devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to V
network, as shown in Figure 15-1, is suggested.
FIGURE 15-2:
DS41249E-page 110
DD
V
has reached a high enough level for proper
DD
POR.
PARM
DD
R1
1 kΩ (or greater)
C1
0.1 μF
(optional, not critical)
is below the re-arming point for the minimum
At this point, a 1 μs (typical) delay will be ini-
) for at least the minimum required time.
POWER-ON RESET
MASTER CLEAR (MCLR)
POR.
DD
DD
drops below a preset re-arming volt-
to continue to ramp to a voltage
RECOMMENDED MCLR
CIRCUIT
DD
returns to a value greater
DD
RA3/MCLR/V
reaches V
DD
PIC16F785/HV785
. The use of an RC
DD
is required. See
PP
BOR
(see
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word. When cleared,
MCLR is internally tied to V
Pull-up is enabled for the MCLR pin. The V
of the RA3/MCLR/V
the internal MCLR option.
15.2.3
The Power-up Timer provides a fixed 64 ms (nominal)
time out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the 31 kHz
LFINTOSC oscillator. For more information, see
Section 3.4 “Internal Clock Modes”. The chip is kept
in Reset as long as PWRT is active. The PWRT delay
allows the V
uration bit, PWRTE can disable (if ‘1’) or enable (if ‘0’)
the Power-up Timer. The Power-up Timer should be
enabled when Brown-out Reset is enabled, although it
is not required.
The Power-up Time Delay will vary from chip-to-chip
and vary due to:
• V
• Temperature variation
• Process variation
See
“Electrical Specifications”).
15.2.4
The BOREN0 and BOREN1 bits in the Configuration
Word select one of four BOR modes. Two modes have
been added to allow software or hardware control of
the BOR enable. When BOREN<1:0> = 01, the SBO-
REN bit of the PCON Register enables/disables the
BOR allowing it to be controlled in software. By select-
ing BOREN<1:0>, the BOR is automatically disabled in
Sleep to conserve power, and enabled on wake-up. In
this mode, the SBOREN bit is disabled. See
Register 15.2 for the Configuration Word definition.
If V
(T
tions”, the Brown-out situation will reset the device.
This will occur regardless of the V
is not assured if V
parameter (T
On any Reset (Power-on, Brown-out Reset, Watchdog,
etc.), the chip will remain in Reset until V
V
be invoked, if enabled, and will keep the chip in Reset
an additional 64 ms.
If V
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once V
rises above V
64 ms Reset.
BOR
BOR
Note:
DD
DD
DD
), see Section 19.0 “Electrical Specifica-
(see Figure 15-3). The Power-up Timer will now
DC
drops below V
variation
falls below V
POWER-UP TIMER (PWRT)
BROWN-OUT RESET (BOR)
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word.
DD
parameters
BOR
BOR
to rise to an acceptable level. A config-
).
, the Power-up Timer will execute a
DD
PP
BOR
BOR
falls below V
pin is not affected by selecting
© 2008 Microchip Technology Inc.
while the Power-up Timer is
for
for greater than parameter
DD
details
and an internal Weak
DD
slew rate. A Reset
BOR
DD
(Section 19.0
for less than
rises above
PP
function
DD