PIC18F2320-I/SO Microchip Technology, PIC18F2320-I/SO Datasheet - Page 383

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: IC MCU FLASH 4KX16 EEPROM 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-I/SO

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 2 x 8 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / Rohs Status: Details

E
ECCP ............................................................................... 141
Effects of Power-Managed Modes on
Electrical Characteristics .................................................. 305
Enhanced Capture/Compare/PWM (ECCP) .................... 141
Enhanced CCP Auto-Shutdown ....................................... 149
Enhanced PWM Mode. See PWM (ECCP Module). ........ 143
Equations
Errata ................................................................................... 5
External Clock Input ........................................................... 21
F
Fail-Safe Clock Monitor ............................................ 237, 249
Fast Register Stack ............................................................ 56
Firmware Instructions ....................................................... 257
Flash Program Memory ...................................................... 71
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 278
H
Hardware Multiplier ............................................................ 85
HSPLL ................................................................................ 20
© 2007 Microchip Technology Inc.
Auto-Shutdown ........................................................ 149
Capture and Compare Modes .................................. 142
Outputs .................................................................... 142
Standard PWM Mode ............................................... 142
Start-up Considerations ........................................... 151
Various Clock Sources ............................................... 28
Capture Mode. See Capture (ECCP Module).
PWM Mode. See PWM (ECCP Module).
16 x 16 Signed Multiplication Algorithm ..................... 86
16 x 16 Unsigned Multiplication Algorithm ................. 86
A/D Acquisition Time ................................................ 216
A/D Minimum Holding Capacitor .............................. 216
Interrupts in Power-Managed Modes ....................... 251
POR or Wake from Sleep ........................................ 251
WDT During Oscillator Failure ................................. 249
Associated Registers ................................................. 79
Control Registers ....................................................... 72
Erase Sequence ........................................................ 76
Erasing ....................................................................... 76
Operation During Code-Protect ................................. 79
Reading ...................................................................... 75
TABLAT Register ....................................................... 74
Table Pointer .............................................................. 74
Table Pointer Boundaries .......................................... 74
Table Reads and Table Writes .................................. 71
Unexpected Termination of Write Operation .............. 79
Write Verify ................................................................ 79
Writing to .................................................................... 77
Introduction ................................................................ 85
Operation ................................................................... 85
Performance Comparison .......................................... 85
And Automatic Restart ..................................... 151
Calculating the Minimum Required
Boundaries Based on Operation ........................ 74
Acquisition Time ...................................... 216
PIC18F2220/2320/4220/4320
I
I/O Ports ........................................................................... 101
I
ID Locations ..............................................................237, 255
INCF ................................................................................ 278
INCFSZ ............................................................................ 279
In-Circuit Debugger .......................................................... 255
In-Circuit Serial Programming (ICSP) .......................237, 255
Indirect Addressing
Indirect Addressing Operation ........................................... 67
Indirect File Operand ......................................................... 59
INFSNZ ............................................................................ 279
Initialization Conditions for all Registers .......................46–49
Instruction Cycle ................................................................ 57
Instruction Flow/Pipelining ................................................. 57
Instruction Format ............................................................ 259
Instruction Set .................................................................. 257
2
C Mode
ACK Pulse ........................................................168, 169
Acknowledge Sequence Timing .............................. 188
Baud Rate Generator .............................................. 181
Bus Collision During a Repeated
Bus Collision During a Start Condition ..................... 190
Bus Collision During a Stop Condition ..................... 193
Clock Arbitration ...................................................... 182
Clock Stretching ....................................................... 174
Effect of a Reset ...................................................... 189
General Call Address Support ................................. 178
Master Mode ............................................................ 179
Master Mode (Reception, 7-Bit Address) ................. 187
Master Mode Operation ........................................... 180
Master Mode Reception ........................................... 185
Master Mode Repeated Start Condition Timing ....... 184
Master Mode Start Condition Timing ....................... 183
Master Mode Transmission ..................................... 185
Multi-Master Communication, Bus Collision
Multi-Master Mode ................................................... 189
Operation ................................................................. 168
Operation in Power-Managed Mode ........................ 189
Read/Write Bit Information (R/W Bit) ................168, 169
Registers ................................................................. 164
Serial Clock (RC3/SCK/SCL) ................................... 169
Slave Mode .............................................................. 168
Stop Condition Timing ............................................. 188
INDF and FSR Registers ........................................... 66
Operation ................................................................... 66
ADDLW .................................................................... 263
ADDWF .................................................................... 263
ADDWFC ................................................................. 264
ANDLW .................................................................... 264
ANDWF .................................................................... 265
BC ............................................................................ 265
BCF ......................................................................... 266
BN ............................................................................ 266
BNC ......................................................................... 267
BNN ......................................................................... 267
BNOV ...................................................................... 268
BNZ ......................................................................... 268
BOV ......................................................................... 271
BRA ......................................................................... 269
BSF .......................................................................... 269
Start Condition ................................................. 192
and Bus Arbitration .......................................... 189
Addressing ....................................................... 168
Reception ........................................................ 169
Transmission ................................................... 169
DS39599G-page 381