PIC18F2320-I/SO Microchip Technology, PIC18F2320-I/SO Datasheet - Page 210

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: IC MCU FLASH 4KX16 EEPROM 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-I/SO

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 2 x 8 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / Rohs Status: Details

PIC18F2220/2320/4220/4320
18.4.2
Once Synchronous mode is selected, reception is
enabled
(RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data
is sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit, SREN, is set, only a single word
is received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
3.
FIGURE 18-8:
TABLE 18-9:
DS39599G-page 208
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
SPBRG
Legend: x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1:
Name
RC7/RX/DT pin
Note:
RC6/TX/CK pin
Initialize the SPBRG register for the appropriate
baud rate (Section 18.2 “USART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
Ensure bits, CREN and SREN, are clear.
(Interrupt)
Write to
bit SREN
SREN bit
CREN bit
RCIF bit
RXREG
by
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
Read
The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear.
USART SYNCHRONOUS MASTER
RECEPTION
USART Receive Register
PSPIE
PSPIP
Baud Rate Generator Register
PSPIF
SPEN
CSRC
GIEH
Bit 7
GIE/
setting
Q2
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
(1)
(1)
(1)
‘0’
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
PEIE/
GIEL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
either
TMR0IE INT0IE
SREN
enable
bit 0
TXEN
RCIF
RCIE
RCIP
Bit 5
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
bit,
CREN ADDEN
SYNC
Bit 4
TXIF
TXIE
TXIP
SREN
bit 2
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
—
bit 3
TMR0IF INT0IF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111 1111 1111
BRGH
FERR
Bit 2
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
If interrupts are desired, set enable bit, RCIE.
If 9-bit reception is desired, set bit, RX9.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
Interrupt flag bit, RCIF, will be set when
reception is complete and an interrupt will be
generated if the enable bit, RCIE, was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit, CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit 4
OERR
TRMT
Bit 1
bit 5
RX9D
TX9D
RBIF
Bit 0
© 2007 Microchip Technology Inc.
bit 6
0000 000x 0000 000u
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
POR, BOR
Value on
bit 7
Q1 Q2 Q3 Q4
Value on
all other
Resets
‘0’