PIC18F2320-I/SO Microchip Technology, PIC18F2320-I/SO Datasheet - Page 222

• Manufacturer Part Number: PIC18F2320-I/SO
• Description: IC MCU FLASH 4KX16 EEPROM 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-I/SO

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SPI, I2C, USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 2 x 8 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MIL
• Lead Free Status / Rohs Status: Details

PIC18F2220/2320/4220/4320
19.8
An A/D conversion can be started by the “Special Event
Trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as ‘1011’ and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the GO/
DONE bit will be set, starting the A/D acquisition and
conversion and the Timer1 (or Timer3) counter will be
reset to zero. Timer1 (or Timer3) is reset to automati-
cally repeat the A/D acquisition period with minimal
software overhead (moving ADRESH/ADRESL to the
TABLE 19-2:
DS39599G-page 220
INTCON
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
PORTA
TRISA
PORTB
TRISB
LATB
PORTE
TRISE
LATE
Legend:
Note 1:
Name
(2)
(2)
2:
3:
(2)
Use of the CCP2 Trigger
Read PORTB pins, Write LATB Latch
PORTB Data Direction Register
PORTB Output Data Latch
TRISA7
A/D Result Register High Byte
A/D Result Register Low Byte
x = unknown, u = unchanged, - = unimplemented, read as ‘0’, q = value depends on condition.
Shaded cells are not used for A/D conversion.
The RE3 port bit is available as an input-only pin only in 40-pin devices and when Master Clear functionality is disabled
(CONFIG3H<7>=
This register is not implemented on PIC18F2X20 devices and reads back 0x00.
These pins may be configured as port pins depending on the oscillator mode selected.
OSCFIE
OSCFIP
OSCFIF
PSPIE
PSPIP
PSPIF
ADFM
RA7
GIEH
Bit 7
GIE/
IBF
—
—
—
—
(4)
(4)
SUMMARY OF A/D REGISTERS
TRISA6
RA6
PEIE/
CMIF
CMIE
CMIP
ADIE
ADIP
GIEL
ADIF
Bit 6
OBE
—
—
—
—
—
(4)
0
(4)
).
TMR0IE
VCFG1
ACQT2
CHS3
RCIE
RCIP
IBOV
RCIF
Bit 5
RA5
—
—
—
—
—
PSPMODE
VCFG0
ACQT1
INT0IE
CHS3
Bit 4
TXIF
TXIE
TXIP
EEIF
EEIE
EEIP
RA4
—
—
PORTE Output Data Latch
PCFG3
ACQT0
SSPIE
SSPIP
SSPIF
BCLIF
BCLIE
BCLIP
RE3
CHS1
RBIE
Bit 3
RA3
—
(1)
Read PORTE pins, Write LATE
PORTE Data Direction
TMR0IF
CCP1IE
CCP1IP
CCP1IF
PCFG2
ADCS2
LVDIE
LVDIP
LVDIF
CHS0
desired location). The appropriate analog input chan-
nel must be selected and the minimum acquisition
period is either timed by the user or an appropriate
T
sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared), the
“Special Event Trigger” will be ignored by the A/D
module but will still reset the Timer1 (or Timer3)
counter.
Bit 2
RA2
ACQ
time, selected before the “Special Event Trigger”,
GO/DONE
TMR2IF
TMR2IE
TMR2IP
TMR3IF
TMR3IE
TMR3IP
PCFG1
ADCS1
INT0IF
Bit 1
RA1
TMR1IE
TMR1IP
TMR1IF
CCP2IF
CCP2IE
CCP2IP
PCFG0
ADCS0
ADON
Bit 0
RBIF
RA0
© 2007 Microchip Technology Inc.
(4)
0000 0000
0000 0000
0000 0000
1111 1111
00-0 0000
00-0 0000
11-1 1111
xxxx xxxx
xxxx xxxx
--00 0000
--00 0qqq
0-00 0000
--0x 0000
--11 1111
xxxx xxxx
1111 1111
xxxx xxxx
---- xxxx
0000 -111
---- -xxx
POR, BOR
Value on
0000 0000
0000 0000
0000 0000
1111 1111
00-0 0000
00-0 0000
11-1 1111
uuuu uuuu
uuuu uuuu
--00 0000
--00 0qqq
0-00 0000
--0u 0000
--11 1111
uuuu uuuu
1111 1111
uuuu uuuu
---- uuuu
0000 -111
---- -uuu
Value on
all other
Resets