PIC18F2320-I/SO Microchip Technology, PIC18F2320-I/SO Datasheet
PIC18F2320-I/SO
Specifications of PIC18F2320-I/SO
Related parts for PIC18F2320-I/SO
PIC18F2320-I/SO Summary of contents
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... PIC18F2220/2320/4220/4320 Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology © 2007 Microchip Technology Inc. 28/40/44-Pin High-Performance, Data Sheet DS39599G ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Secondary Oscillator using Timer1 @ 32 kHz • Fail-Safe Clock Monitor - Allows for safe shutdown if peripheral clock stops Program Memory Device Flash # Single Word (bytes) Instructions PIC18F2220 4096 2048 PIC18F2320 8192 4096 PIC18F4220 4096 2048 PIC18F4320 8192 4096 © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Peripheral Highlights: • ...
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... RA1/AN1 3 38 -/CV 4 REF REF RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 * RB3/AN9/CCP2 RB2/AN8/INT2 RB1/AN10/INT1 RB0/AN12/INT0 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/AN11/KBI0 RB3/AN9/CCP2* RB2/AN8/INT2 RB1/AN10/INT1 RB0/AN12/INT0 RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 © 2007 Microchip Technology Inc. ...
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... RB2/AN8/INT2 RB3/AN9/CCP2* * RB3 is the alternate pin for the CCP2 pin multiplexing. 44-Pin QFN RC7/RX/DT RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/AN12/INT0 RB1/AN10/INT1 RB2/AN8/INT2 * RB3 is the alternate pin for the CCP2 pin multiplexing. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 RC0/T1OSO/T1CKI OSC2/CLKO/RA6 3 OSC1/CLKI/RA7 30 4 PIC18F4220 ...
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... Appendix E: Migration from Mid-range to Enhanced Devices............................................................................................................ 378 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 378 Index .................................................................................................................................................................................................. 379 The Microchip Web Site ..................................................................................................................................................................... 389 Customer Change Notification Service .............................................................................................................................................. 389 Customer Support .............................................................................................................................................................................. 389 Reader Response .............................................................................................................................................................................. 390 PIC18F2220/2320/4220/4320 Product Identification System ............................................................................................................ 391 DS39599G-page 4 © 2007 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599G-page 5 ...
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... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 6 © 2007 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F2220 • PIC18F4220 • PIC18F2320 • PIC18F4320 This family offers the advantages of all PIC18 micro- controllers – namely, high computational performance at an economical price with the addition of high- endurance Enhanced Flash program memory. On top ...
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... PIC18F4X20 devices) Kbytes for All other features for devices in this family are identical. These are summarized in Table 1-1. The pinouts for all devices are listed in Table 1-2 and Table 1-3. PIC18F2220 PIC18F2320 DC – 40 MHz DC – 40 MHz 4096 8192 2048 4096 512 ...
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... Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of the CCPMX2 Configuration bit. 2: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Data Bus<8> ...
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... RB2/AN8/INT2 (1) RB3/AN9/CCP2 RB4/AN11/KBI0 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T1CKI (1) RC1/T1OSI/CCP2 RC2/CCP1/P1A RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD 8 RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D PORTE RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS (2) RE3 10-Bit A/D Converter Data EEPROM (256 Bytes) © 2007 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-drain (no diode to V Note 1: Alternate assignment for CCP2 when CCP2MX is cleared. 2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Buffer Type Type Master Clear (input) or programming voltage (input Master Clear (Reset) input ...
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... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power ) DD Description © 2007 Microchip Technology Inc. ...
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... ST = Schmitt Trigger input with CMOS levels O = Output OD = Open-drain (no diode to V Note 1: Alternate assignment for CCP2 when CCP2MX is cleared. 2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Buffer Type Type PORTC is a bidirectional I/O port. I/O ST Digital I/O ...
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... I/O TTL Digital I/O. I Analog Analog input 4. I TTL SPI slave select input. I Analog Low-Voltage Detect input. O — Comparator 2 output. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. CMOS = CMOS compatible input or output I = Input P = Power ) DD Description © 2007 Microchip Technology Inc. ...
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... O = Output OD = Open-drain (no diode to V Note 1: Alternate assignment for CCP2 when CCP2MX is cleared. 2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. ...
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... Digital I/O. O — USART asynchronous transmit. I/O ST USART synchronous clock (see related RX/DT). 1 I/O ST Digital I/ USART asynchronous receive. I/O ST USART synchronous data (see related TX/CK). CMOS = CMOS compatible input or output I = Input P = Power ) DD Description 2 C™ mode. © 2007 Microchip Technology Inc. ...
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... O = Output OD = Open-drain (no diode to V Note 1: Alternate assignment for CCP2 when CCP2MX is cleared. 2: Default assignment for CCP2 when CCP2MX (CONFIG3H<0>) is set. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Pin Buffer Type Type PORTD is a bidirectional I/O port or a Parallel Slave Port (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when PSP module is enabled ...
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... RD and WR). 18 — — See MCLR/V /RE3 pin — Ground reference for logic and I/O pins — Positive supply for logic and I/O pins connect. 28 CMOS = CMOS compatible input or output I = Input P = Power ) DD Description © 2007 Microchip Technology Inc. ...
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... OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a fre- quency out of the crystal manufacturers specifications. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 FIGURE 2-1: (1) C1 (1) C2 Note 1: See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... Configuration Register 1H when DD OSC2 HS Mode Crystal OSC1 Osc of external EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) OSC2 Open PLL BLOCK DIAGRAM HS Osc Enable PLL Enable Phase F IN Comparator F OUT Loop Filter ÷4 VCO SYSCLK © 2007 Microchip Technology Inc. ...
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... CONFIGURATION) OSC1/CLKI Clock from Ext. System PIC18FXXXX RA6 I/O (OSC2) © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 2.5 RC Oscillator For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (R ues and the operating temperature ...
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... INTIO1 mode – The OSC2 pin outputs FOSC/4 while OSC1 functions as RA7 for digital input and output. • INTIO2 mode – OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output. register © 2007 Microchip Technology Inc. ...
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... TUN<0>: A placeholder with no effect on the INTRC frequency. Provided to facilitate incrementation and decrementation of the OSCTUN2 register and adjustment of the INTRC frequency. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 When the OSCTUNE register is modified, the INTOSC and INTRC frequencies begin shifting to the new fre- quency. The INTOSC and INTRC clocks will stabilize at the new frequency within 100 μ ...
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... This includes the WDT, Fail-Safe Clock Monitor and peripherals. R/W-0 R/W-0 R/W-0 TUN4 TUN3 TUN2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 TUN1 TUN0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... Figure 2-8. See Section 12.0 “Timer1 Module” for further details of the Timer1 oscillator. See Section 23.1 “Configuration Bits” for Configuration register details. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 2.7.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 2-3) controls sev- eral aspects of the system clock’ ...
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... Other Modules OSCCON<6:4> 8 MHz 111 4 MHz 110 2 MHz 101 1 MHz 100 500 kHz 8 MHz 011 (INTOSC) 250 kHz 010 125 kHz 001 31 kHz 000 Clock OSCCON<1:0> Control Peripherals T1OSC Internal Oscillator CPU IDLEN WDT, FSCM © 2007 Microchip Technology Inc. ...
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... SCS1:SCS0: System Clock Select bits 1x = Internal oscillator block (RC modes Timer1 oscillator (Secondary modes Primary oscillator (Sleep and PRI_IDLE modes) Note 1: Depends on state of IESO bit in Configuration Register 1H. 2: SCS0 may not be set while T1OSCEN (T1CON<3>) is clear. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 (1) R/W-0 R R-0 IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘ ...
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... Floating, pulled by external clock Floating, pulled by external clock Feedback inverter disabled at quiescent voltage level OSC2 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level © 2007 Microchip Technology Inc. ...
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... RC_IDLE 1 1x Note 1: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 For PIC18F2X20/4X20 devices, the power-managed modes are invoked by using the existing SLEEP instruction. All modes exit to PRI_RUN mode when trig- gered by an interrupt, a Reset WDT time-out (PRI_RUN mode is the normal full-power execution mode ...
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... SCS bits are unchanged during and after the wake-up. Figure 3-2 shows how the system is clocked during the clock source switch. The example assumes the device was in SEC_IDLE or SEC_RUN mode when a wake is triggered (the primary clock was configured in HSPLL mode). © 2007 Microchip Technology Inc ...
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... Clearing IDLEN allows the CPU to be clocked. Setting IDLEN disables clocks to the CPU, effectively stopping program execution (see Register 2-3). The peripherals continue to be clocked regardless of the setting of the IDLEN bit. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 WDT Peripherals are Time-out Clocked by ...
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... TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) OSC1 (1) T OST PLL Clock Output CPU Clock Peripheral Clock Program PC Counter Wake-up Event Note 1024 (approx). These intervals are not shown to scale. OST OSC PLL DS39599G-page PLL ( OSTS bit Set © 2007 Microchip Technology Inc. ...
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... Peripheral Clock Program PC Counter Wake-up Event © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 When a wake-up event occurs, the CPU is clocked from the primary clock source. A delay of approxi- mately 10 μs is required between the wake-up event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. ...
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... T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run Clock Transition PLL ( Clock Transition OSTS bit Set © 2007 Microchip Technology Inc. ...
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... These intervals are not shown to scale. OST OSC PLL © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear ...
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... Figure 3-6). When the clock switch is complete, the Timer1 oscillator is disabled, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the system clock. The IDLEN and SCS bits are not affected by the wake-up Clock Transition © 2007 Microchip Technology Inc. ...
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... INTRC OSC1 CPU Clock Peripheral Clock Program PC Counter © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note: Caution should be used when modifying a single IRCF bit possible to select a higher clock speed than is supported by the low V Improper device operation may result if the V If the IRCF bits are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear ...
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... On all exits from Lower Power mode by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON<7>) is set. Other- wise, code execution continues or resumes without branching (see Section 9.0 “Interrupts”). © 2007 Microchip Technology Inc. ...
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... Execution continues during the INTOSC stabilization period. 5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other required delays (see Section 3.3 “Idle Modes”). © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Clock Ready Power-Managed ...
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... INTRC clock source is selected. Being able to adjust the INTOSC requires knowing when an adjustment is required, in which direction it should be made and in some cases, how large a change is needed. Three examples are shown but other techniques may be used. © 2007 Microchip Technology Inc. ...
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... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast – decrement OSCTUNE. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 3.6.3 EXAMPLE – CCP IN CAPTURE MODE ...
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... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 42 © 2007 Microchip Technology Inc. ...
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... INTRC Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-1 for time-out situations. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Most registers are not affected by a WDT wake-up since this is viewed as the resumption of normal oper- ation ...
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... D005) for BOR (parameter #35), the brown-out situ- DD for less than T . The chip will BOR rises above BOR ; it then will keep the chip in BOR (parameter PWRT while the Power-up BOR , the Power-up Timer will execute BOR © 2007 Microchip Technology Inc. ...
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... Legend unchanged unknown unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 (2) Power-up and Brown-out ...
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... --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu (1) uuuu uuuu (1) uuuu -u-u (1) uu-u u-uu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A © 2007 Microchip Technology Inc. ...
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... See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 MCLR Resets Power-on Reset, ...
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... Microchip Technology Inc. ...
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... See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 MCLR Resets Power-on Reset, ...
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... PWRT Time-out OST Time-out Internal Reset FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR Internal POR PWRT Time-out OST Time-out Internal Reset DS39599G-page 50 T PWRT T OST T PWRT T OST T PWRT T OST © 2007 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED MCLR Internal POR PWRT Time-out OST Time-out PLL Time-out Internal Reset Note 1024 clock cycles. OST ≈ max. First three stages of the PWRT timer. T PLL © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 , V RISE > PWRT T OST T PWRT T ...
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... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 52 © 2007 Microchip Technology Inc. ...
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... Kbytes of Flash memory and can store up to 4,096 single-word instructions. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The Program Memory Maps for PIC18F2220/4220 and PIC18F2320/4320 devices are shown in Figure 5-1 and Figure 5-2, respectively. FIGURE 5-2: PC<20:0> CALL,RCALL,RETURN ...
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... This is not the same as a Reset, as the contents of the SFRs are not affected. Return Address Stack 11111 11110 11101 STKPTR<4:0> TOSL 34h 00011 001A34h Top-of-Stack 00010 000D58h 00001 00000 00010 © 2007 Microchip Technology Inc. ...
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... POP instruction. The POP instruc- tion discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-0 R/W-0 ...
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... LSB of PCL is fixed to a value of ‘0’. The PC increments address sequential instructions in the program memory. The CALL, GOTO and program branch RCALL, instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. © 2007 Microchip Technology Inc. ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 5.6 Instruction Flow/Pipelining An “ ...
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... Execute this word as a NOP REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2007 Microchip Technology Inc. ...
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... Data is transferred to/from program memory, one byte at a time. The Table Read/Table Write operation is discussed further in Section 6.1 “Table Reads and Table Writes”. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 5.9 Data Memory Organization The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory ...
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... The BSR is ignored and the Access Bank is used. The first 128 bytes are general purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the bank used by the instruction. © 2007 Microchip Technology Inc. ...
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... Legend: — = Unimplemented registers, read as ‘0’. Note 1: This register is not available on PIC18F2X20 devices. 2: This is not a physical register. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 “core” are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. ...
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... DC C 47, 68 ---x xxxx 47, 119 0000 0000 47, 119 xxxx xxxx T0PS1 T0PS0 47, 117 1111 1111 © 2007 Microchip Technology Inc. ...
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... Reset. 5: These registers and/or bits are not implemented on the PIC18F2X20 devices and read as 0x00. 6: The RE3 port bit is available as an input only pin only in 40-pin devices when Master Clear functionality is disabled (CONFIG3H<7> = 0). © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Bit 4 Bit 3 Bit 2 ...
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... Note 1: For register file map detail, see Table 5-1. 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 5.11 Bank Select Register (BSR) The need for a large general purpose memory space dictates a RAM banking scheme ...
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... NOP (Status bits are not affected Indirect Addressing write is performed when the target address is an FSRnH or FSRnL register, the data is written to the FSR register but no pre post-increment/decrement is performed. will be incremented © 2007 Microchip Technology Inc. ...
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... INDIRECT ADDRESSING OPERATION Instruction Executed Opcode BSR<3:0> Instruction Fetched Opcode FIGURE 5-9: INDIRECT ADDRESSING 3 11 Note 1: For register file map detail, see Table 5-1. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 0h RAM Address FFFh 12 File Address = access of an Indirect Addressing register File ...
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... For other instructions not affecting any Status bits (see Table 24-2). Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. R/W-x R/W-x R/W Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-x R/W-x (1) ( bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... BOR: Brown-out Reset Status bit Brown-out Reset has not occurred (set by firmware only Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note 1: If the BOREN Configuration bit is set (Brown-out Reset enabled), the BOR bit is ‘ ...
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... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 70 © 2007 Microchip Technology Inc. ...
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... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 The program memory space is 16 bits wide while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces DD through an 8-bit register (TABLAT) ...
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... Program memory is read using table read instructions. See Section 6.3 “Reading the Flash Program Memory” regarding table reads. Note: Interrupt flag bit, EEIF in the PIR2 register, is set when the write is complete. It must be cleared in software. © 2007 Microchip Technology Inc. TABLAT ...
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... Initiates a memory read (Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 Read completed Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-x R/W-0 (1) ...
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... The Least Significant bits (TBLPTR<5:0>) are ignored. Figure 6-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTRH 8 7 LONG WRITE – TBLPTR<21:3> READ or WRITE – TBLPTR<21:0> TBLPTRL 0 © 2007 Microchip Technology Inc. ...
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... TBLRD*+ MOVFW TABLAT MOVWF WORD_ODD © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT ...
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... Execute a NOP. 9. Re-enable interrupts. ; load TBLPTR with the base ; address of the memory block ; point to Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55H ; write AAH ; start erase (CPU stall) ; re-enable interrupts © 2007 Microchip Technology Inc. ...
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... CFGS bit to access program memory; • set WREN bit to enable byte writes. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction has to be executed 8 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written ...
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... FSR0 ; present data to table latch ; short write ; to internal TBLWT holding register, increment TBLPTR ; loop until buffers are full © 2007 Microchip Technology Inc. ...
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... PIE2 OSCFIE CMIE — Legend unknown unchanged reserved unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 ; disable interrupts ; required sequence ; write 55H ; write AAH ; start program (CPU stall) ; re-enable interrupts ...
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... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 80 © 2007 Microchip Technology Inc. ...
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... Control bit EEPGD determines if the access will be to program or data EEPROM memory. When clear, oper- ations will access the data EEPROM memory. When set, program memory is accessed. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data EEPROM memory ...
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... When a WRERR occurs, the EEPGD or FREE bits are not cleared. This allows tracing of the error condition. DS39599G-page 82 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/S-0 R/S bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... BSF INTCON, GIE SLEEP BCF EECON1, WREN © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruc- tion ...
Page 86
... POR, BOR Resets RBIF 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 — — RD xx-0 x000 uu-0 u000 CCP2IP 11-1 1111 ---1 1111 CCP2IF 00-0 0000 ---0 0000 CCP2IE 00-0 0000 ---0 0000 © 2007 Microchip Technology Inc. ...
Page 87
... Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 8.2 Operation Example 8-1 shows the sequence unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. ...
Page 88
... MOVF ARG2H, W SUBWFB RES3 ; CONT_CODE : SIGNED MULTIPLICATION ALGORITHM SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ARG1L * ARG2H -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ; ARG1H * ARG2L -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ; ARG1H:ARG1L neg? ; no, done ; ; ; © 2007 Microchip Technology Inc. ...
Page 89
... INTERRUPTS The PIC18F2320/4320 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 000008h and the low-priority interrupt vec- tor is at 000018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress ...
Page 90
... INT2IF INT2IE INT2IP IPE IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP © 2007 Microchip Technology Inc. Wake- Power-Managed Mode Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h PEIE/GIEL ...
Page 91
... None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note: Interrupt flag bits are set when an interrupt ...
Page 92
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39599G-page 90 R/W-1 U-0 R/W-1 — INTEDG2 TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-1 — RBIP bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 93
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 ...
Page 94
... R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) © 2007 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 95
... A TMR1 or TMR3 register capture occurred (must be cleared in software TMR1 or TMR3 register capture occurred Compare mode TMR1 or TMR3 register compare match occurred (must be cleared in software TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-0 R/W-0 EEIF BCLIF LVDIF U = Unimplemented bit, read as ‘ ...
Page 96
... Disables the TMR1 overflow interrupt Note 1: This bit is reserved on PIC18F2X20 devices; always maintain this bit clear. DS39599G-page 94 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 97
... Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-0 R/W-0 EEIE BCLIE LVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 ...
Page 98
... Low priority Note 1: This bit is reserved on PIC18F2X20 devices; always maintain this bit set. DS39599G-page 96 R/W-1 R/W-1 R/W-1 TXIP SSPIP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 99
... Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-1 R/W-1 R/W-1 EEIP BCLIP LVDIP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 100
... A Brown-out Reset has not occurred (set by firmware only Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) DS39599G-page 98 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 POR BOR bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 101
... USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 9.8 PORTB Interrupt-on-Change An input change on PORTB<7:4> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2< ...
Page 102
... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 100 © 2007 Microchip Technology Inc. ...
Page 103
... PORT Note 1: I/O pins have diode protection to V © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 10.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 104
... I/O pins have protection diodes to V and BLOCK DIAGRAM OF RA4/T0CKI PIN D Q (1) Q I/O pin CK N Data Latch Schmitt CK Q Trigger TRIS Latch Input Buffer and BLOCK DIAGRAM OF RA7 PIN To Oscillator (1) N I/O pin TTL Input Buffer and © 2007 Microchip Technology Inc. ...
Page 105
... Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Buffer Function TTL Input/output or analog input ...
Page 106
... From other EN RB7:RB5 and RB4 pins RB7:RB5 in Serial Programming Mode Note 1: I/O pins have diode protection enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). © 2007 Microchip Technology Inc Weak P Pull-up (1) I/O pin ST Buffer Q1 RD PORTB ...
Page 107
... PORTB CK Data Latch D WR TRISB CK TRIS Latch RD TRISC RD PORTB CCP2 Input Analog Input Mode To A/D Converter Note 1: I/O pins have diode protection to V © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 FIGURE 10- (2) RBPU Weak P Pull-up Data Bus WR LATB (1) or PORTB I/O pin ...
Page 108
... POR, BOR Resets RB0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 RBIF 0000 000x 0000 000u RBIP 1111 -1-1 1111 -1-1 INT1IF 11-0 0-00 11-0 0-00 PCFG0 --00 0000 --00 0000 © 2007 Microchip Technology Inc. ...
Page 109
... I/O pins have diode protection Port/Peripheral Select signal selects between port data (output) and peripheral output. 3: Peripheral Output Enable is only active if Peripheral Select is active. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note Power-on Reset, these pins are configured as digital inputs. The contents of the TRISC register are affected by peripheral overrides ...
Page 110
... USART synchronous data. Bit 4 Bit 3 Bit 2 Bit 1 RC4 RC3 RC2 RC1 2 C™ mode). Value on Value on Bit 0 all other POR, BOR Resets RC0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 © 2007 Microchip Technology Inc. ...
Page 111
... RD TRISD RD PORTD PSP Write Note 1: I/O pins have diode protection to V © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 PORTD can also be configured as an 8-bit wide micro- processor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. See Section 10.6 “Parallel Slave Port” ...
Page 112
... V SS TTL Buffer Schmitt Trigger Input Buffer Value on Value on Bit 0 all other POR, BOR Resets RD0 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 -111 0000 -111 0000 0000 0000 0000 © 2007 Microchip Technology Inc. ...
Page 113
... Otherwise, it functions as the device’s Master Clear input. In either configuration, RE3 also functions as the programming voltage input during programming. Note Power-on Reset, RE3 is enabled as a digital input only if Master Clear functionality is disabled. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 EXAMPLE 10-5: CLRF PORTE CLRF LATE MOVLW ...
Page 114
... Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output DS39599G-page 112 MCLR RE3 R/W-0 U-0 R/W-1 PSPMODE — TRISE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TRISE1 TRISE0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 115
... Shaded cells are not used by PORTE. Note 1: The RE3 port bit is available as an input-only pin only in 40-pin devices and when Master Clear functionality is disabled (CONFIG3H<7>=0). © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Function (1) Input/output port pin, analog input or read control input in Parallel Slave Port mode ...
Page 116
... Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pins have diode protection to V PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) One bit of PORTD D Q RDx pin CK TTL PORTE Pins Read RD TTL Chip Select CS TTL Write WR TTL and © 2007 Microchip Technology Inc. ...
Page 117
... ADIF RCIF PIE1 PSPIE ADIE RCIE IPR1 PSPIP ADIP RCIP ADCON1 — — VCFG1 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Bit 4 Bit 3 Bit 2 Bit 1 — ...
Page 118
... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 116 © 2007 Microchip Technology Inc. ...
Page 119
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. ...
Page 120
... T0PS2, T0PS1, T0PS0 0 Sync with Internal TMR0L Clocks delay PSA Data Bus 8 TMR0 Set Interrupt Flag bit TMR0IF on Overflow Set Interrupt TMR0 Flag bit TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 Data Bus<7:0> © 2007 Microchip Technology Inc. ...
Page 121
... PORTA Data Direction Register Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in Configuration Word 1H. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “ ...
Page 122
... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 120 © 2007 Microchip Technology Inc. ...
Page 123
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...
Page 124
... T1CKPS1:T1CKPS0 TMR1CS 8 CCP Special Event Trigger CLR TMR1L TMR1ON on/off 1 T1OSCEN F /4 OSC Enable Internal 0 (1) Oscillator Clock TMR1CS T1CKPS1:T1CKPS0 Synchronized 0 Clock Input 1 Synchronize det 2 Peripheral Clocks Synchronized 0 Clock Input 1 T1SYNC Synchronize Prescaler det 2 Peripheral Clocks © 2007 Microchip Technology Inc. ...
Page 125
... Capacitor values are for design guidance only. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 12.3 Timer1 Oscillator Layout Considerations The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity ...
Page 126
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the rou- tine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. © 2007 Microchip Technology Inc. ...
Page 127
... Shaded cells are not used by the Timer1 module. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 ; Preload TMR1 register pair ...
Page 128
... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 126 © 2007 Microchip Technology Inc. ...
Page 129
... Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 13.1 Timer2 Operation Timer2 can be used as the PWM time base for the PWM mode of the CCP module. The TMR2 register is readable and writable and is cleared on any device Reset ...
Page 130
... POR, BOR Resets RBIF 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR1IE 0000 0000 0000 0000 TMR1IP 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 SCS0 0000 qq00 0000 qq00 © 2007 Microchip Technology Inc. ...
Page 131
... Internal clock (F OSC bit 0 TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Figure 14 simplified block diagram of the Timer3 module. Register 14-1 shows the Timer3 Control register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. ...
Page 132
... Oscillator Clock TMR3CS T3CKPS1:T3CKPS0 8 CCP Special Event Trigger T3CCPx TMR3 CLR TMR3L TMR3ON On/Off OSC Internal 0 (1) Clock T3CKPS1:T3CKPS0 TMR3CS Synchronized Clock Input Synchronize det 2 Peripheral Clocks Synchronized 0 Clock Input 1 T3SYNC Synchronize Prescaler det 2 Peripheral Clocks © 2007 Microchip Technology Inc. ...
Page 133
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T3CON RD16 T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 14.4 Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode ...
Page 134
... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 132 © 2007 Microchip Technology Inc. ...
Page 135
... Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin operates as a port pin for input and output) 1011 = Compare mode: trigger special event (CCPxIF bit is set) 11xx = PWM mode © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note: In 28-pin devices, both CCP1 and CCP2 function as standard CCP modules ...
Page 136
... CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable. CCP2 functions identically to CCP1 except for the enhanced PWM modes offered by CCP2 Interaction © 2007 Microchip Technology Inc. ...
Page 137
... Prescaler ÷ CCP2 pin and Edge Detect CCP2CON<3:0> Q’s © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 15.3.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode ...
Page 138
... Set Flag bit CCP1IF Output Logic Match CCP1CON<3:0> Mode Select TMR1H Special Event Trigger Set Flag bit CCP2IF T3CCP1 T3CCP2 Output Logic Match CCP2CON<3:0> Mode Select CCPR1H CCPR1L Comparator 1 0 T3CCP2 TMR1L TMR3H TMR3L 0 1 Comparator CCPR2H CCPR2L © 2007 Microchip Technology Inc. ...
Page 139
... T3CCP2 T3CKPS1 T3CKPS0 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1. Note 1: These bits are reserved on the PIC18F2X20 devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Bit 4 Bit 3 Bit 2 Bit 1 ...
Page 140
... CCPR1H until a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. • OSC (TMR2 Prescale Value) T • (TMR2 Prescale Value) OSC © 2007 Microchip Technology Inc. ...
Page 141
... Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 15.5.3 SETUP FOR PWM OPERATION ...
Page 142
... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 140 © 2007 Microchip Technology Inc. ...
Page 143
... PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR1L. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 The ECCP module differs from the CCP with the addi- tion of an enhanced PWM mode which allows for output channels, user-selectable polarity, dead band control and automatic shutdown and restart ...
Page 144
... PWM Operation” or Section 16.4.7 “Setup for PWM Operation”. The latter is more generic but will work for either single or multi output PWM. RC2 RD5 RD6 CCP1 RD5/PSP5 RD6/PSP6 P1A P1B RD6/PSP6 P1A P1B P1C © 2007 Microchip Technology Inc. RD7 RD7/PSP7 RD6/PSP6 P1D ...
Page 145
... D.C. PR2 Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock or 2 bits of the prescaler to create the 10-bit time base. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 waveforms do not exactly match the standard PWM waveforms but are instead offset by one full instruction cycle ( ...
Page 146
... Delay = (PWM1CON<6:0>) OSC Note 1: Dead band delay is programmed using the PWM1CON register (see Section 16.4.4 “Programmable Dead-Band Delay”). DS39599G-page 144 0 Duty Cycle Period (1) (1) Delay Delay 0 Duty Cycle Period (1) (1) Delay Delay © 2007 Microchip Technology Inc. PR2+1 PR2+1 ...
Page 147
... TRISC<2> and TRISD<5> bits must be cleared to configure P1A and P1B as outputs. FIGURE 16-5: EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) PIC18F4220/4320 Half-Bridge Output Driving a Full-Bridge Circuit PIC18F4220/4320 P1A P1B © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 FIGURE 16-4: Period Duty Cycle (2) P1A td (2) P1B ...
Page 148
... P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2> and PORTD<5:7> data latches. The TRISC<2> and TRISD<5:7> bits must be cleared to make the P1A, P1B, P1C and P1D pins output. Period Duty Cycle Period Duty Cycle (1) (1) © 2007 Microchip Technology Inc. ...
Page 149
... The direction of the PWM output changes when the duty cycle of the output near 100%. 2. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 V+ QA FET Driver ...
Page 150
... Note 1: All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. off DS39599G-page 148 (1) Period DC (Note 2) Forward Period Reverse Period Period (1) DC (3) t off (2, – t off on © 2007 Microchip Technology Inc. ...
Page 151
... PDC6:PDC0: PWM Delay Count bits Delay time, in number of F should transition to active and the actual time it transitions active. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 A shutdown event can be caused by either of the two comparator modules or the INT0 pin (or any combina- tion of these three sources). The comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit ...
Page 152
... Drive Pins B and D to ‘0’ Drive Pins B and D to ‘1’ Pins B and D tri-state DS39599G-page 150 R/W-0 R/W-0 R/W-0 ECCPAS0 PSSAC1 PSSAC0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 PSSBD1 PSSBD0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 153
... Activity Dead Time Duty Cycle Shutdown Event ECCPASE bit © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 16.4.6 START-UP CONSIDERATIONS When the ECCP module is used in the PWM mode, the application hardware must use the proper external pull- up and/or pull-down resistors on the PWM output pins. ...
Page 154
... EFFECTS OF A RESET Both Power-on and subsequent Resets will force all ports to Input mode and the CCP registers to their Reset states. This forces the Enhanced CCP module to reset to a state compatible with the standard CCP module. © 2007 Microchip Technology Inc. is enabled ...
Page 155
... PWM1CON PRSEN PDC6 PDC5 OSCCON IDLEN IRCF2 IRCF1 Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the ECCP module in enhanced PWM mode. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Bit 4 Bit 3 Bit 2 Bit 1 INT0IE RBIE TMR0IF INT0IF RI TO ...
Page 156
... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 154 © 2007 Microchip Technology Inc. ...
Page 157
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. All four ...
Page 158
... SSPIF interrupt is set. During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2007 Microchip Technology Inc. R-0 R bit Bit is unknown ...
Page 159
... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When the MSSP is enabled in SPI mode, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-0 R/W-0 (2) ...
Page 160
... Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. © 2007 Microchip Technology Inc. ...
Page 161
... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.3.4 TYPICAL CONNECTION Register 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
Page 162
... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 5 bit 4 bit 2 bit 1 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...
Page 163
... SSPIF Interrupt Flag SSPSR to SSPBUF © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 is tri-stated, even if in the middle of a transmitted byte. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON1<3:0> = 0100), the SPI module will reset when the SS pin is set high ...
Page 164
... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39599G-page 162 bit 6 bit 5 bit 4 bit 2 bit 3 bit 6 bit 2 bit 5 bit 4 bit 3 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2007 Microchip Technology Inc. ...
Page 165
... Legend unknown unchanged unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X20 devices; always maintain these bits clear. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.3.8.1 Slave in Power-Managed Modes In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device ...
Page 166
... SSPBUF and the SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. © 2007 Microchip Technology Inc. ...
Page 167
... This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 4: ORing this bit with the SSPCON2 bits, SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 2 C™ MODE) R-0 ...
Page 168
... C™ MODE) R/W-0 R/W-0 R/W-0 (1) (2) CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) /(4 * (SSPADD + 1)) OSC (2) (2) R/W-0 R/W-0 (2) (2) (2) SSPM1 SSPM0 bit Bit is unknown 2 C conditions were not valid for a (2) © 2007 Microchip Technology Inc. ...
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... In Slave mode Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled Clock stretching is disabled Note 1: Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 2 C™ MODE) R/W-0 ...
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... Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF. 7. Receive Repeated Start condition. 8. Receive first (high) byte of address (bits, SSPIF and BF, are set). 9. Read the SSPBUF register (clears bit, BF) and clear flag bit, SSPIF. © 2007 Microchip Technology Inc. ...
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... The clock must be released by setting bit, CKP (SSPCON1<4>). See Section 17.4.4 “Clock Stretching” for more detail. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.3.3 Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set ...
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... PIC18F2220/2320/4220/4320 2 FIGURE 17-8: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 7-BIT ADDRESS) DS39599G-page 170 © 2007 Microchip Technology Inc. ...
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... FIGURE 17-9: I C™ SLAVE MODE TIMING (TRANSMISSION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599G-page 171 ...
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... PIC18F2220/2320/4220/4320 2 FIGURE 17-10: I C™ SLAVE MODE TIMING WITH SEN = 0 (RECEPTION, 10-BIT ADDRESS) DS39599G-page 172 © 2007 Microchip Technology Inc. ...
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... FIGURE 17-11: I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599G-page 173 ...
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... R/W bit set to ‘1’. After the third address sequence is performed, the UA bit is not set, the module is now configured in Transmit mode and clock stretching is controlled by the BF flag as in 7-Bit Slave Transmit mode (see Figure 17-11). © 2007 Microchip Technology Inc. ...
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... SDA DX SCL CKP WR SSPCON1 © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 remain low until the CKP bit is set and all other 2 devices on the I C bus have deasserted SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 17-12) ...
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... PIC18F2220/2320/4220/4320 2 FIGURE 17-13: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 7-BIT ADDRESS) DS39599G-page 176 © 2007 Microchip Technology Inc. ...
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... FIGURE 17-14: I C™ SLAVE MODE TIMING WITH SEN = 1 (RECEPTION, 10-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599G-page 177 ...
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... UA bit will not is enabled be set and the slave will begin receiving data after the Acknowledge (Figure 17-15). Address is compared to general call address after ACK, set interrupt R ACK Cleared in software SSPBUF is read Receiving Data ACK ‘0’ ‘1’ © 2007 Microchip Technology Inc. ...
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... Generate a Stop condition on SDA and SCL. FIGURE 17-16: MSSP BLOCK DIAGRAM (I SDA SDA In SCL SCL In Bus Collision © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 Note: The MSSP module, when configured Master mode, does not allow queueing of events. For instance, the user is not ...
Page 182
... SSPCON2 register (SSPCON2<6>). 10. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. 11. The user generates a Stop condition by setting the Stop Enable bit, PEN (SSPCON2<2>). 12. Interrupt is generated once the Stop condition is complete. © 2007 Microchip Technology Inc. ...
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... Actual clock rate will depend on bus conditions. Bus capacitance can increase rise time and extend the low time of the clock period, reducing the effective clock frequency (see Section 17.4.7.2 “Clock Arbitration”). © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.7.1 Baud Rate Generation in ...
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... DX-1 SCL allowed to transition high BRG decrements on Q2 and Q4 cycles 02h 01h 00h (hold off) SCL is sampled high, reload takes place and BRG starts its count 03h 02h © 2007 Microchip Technology Inc. ...
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... C module is reset into its Idle state. FIGURE 17-19: FIRST START BIT TIMING Write to SEN bit occurs here SDA SCL © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.8.1 WCOL Status Flag If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’ ...
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... SSPCON2 is disabled until the Repeated Start condition is complete. Set S (SSPSTAT<3>) SDA = 1, At completion of Start bit, SCL = 1 hardware clears RSEN bit and sets SSPIF BRG BRG BRG Write to SSPBUF occurs here T BRG Sr = Repeated Start 1st bit T BRG © 2007 Microchip Technology Inc. ...
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... SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). WCOL must be cleared in software. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.10.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2<6>) is ...
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... PIC18F2220/2320/4220/4320 2 FIGURE 17-21: I C™ MASTER MODE WAVEFORM (TRANSMISSION 10-BIT ADDRESS) DS39599G-page 186 © 2007 Microchip Technology Inc. ...
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... FIGURE 17-22: I C™ MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 DS39599G-page 187 ...
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... SDA sampled high. P bit (SSPSTAT<4>) is set. PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set T BRG BRG BRG BRG SCL brought high after T BRG SDA asserted low before rising edge of clock to setup Stop condition Cleared in software BRG © 2007 Microchip Technology Inc. ...
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... An Acknowledge Condition FIGURE 17-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA SCL BCLIF © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 17.4.17 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION 2 C module Multi-Master mode support is achieved by bus arbitra- tion ...
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... Repeated Start or Stop conditions. SEN cleared automatically because of bus collision. MSSP module reset into Idle state. SSPIF and BCLIF are cleared in software SSPIF and BCLIF are cleared in software © 2007 Microchip Technology Inc. ...
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... BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION Less than T SDA pulled low by other master. SDA Reset BRG and assert SDA. SCL SEN BCLIF S SSPIF © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 SDA = 0, SCL = BRG BRG SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SDA = 0, SCL = 1 ...
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... Repeated Start condition is complete. Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. Cleared in software T T BRG BRG © 2007 Microchip Technology Inc. ‘0’ ‘0’ Interrupt cleared in software ‘0’ ...
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... SCL PEN BCLIF P SSPIF © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> ...
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... PIC18F2220/2320/4220/4320 NOTES: DS39599G-page 194 © 2007 Microchip Technology Inc. ...
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... TRISC<7> bit must be set (= 1) • TRISC<6> bit must be cleared (= 0) Register 18-1 shows the Transmit Status and Control register (TXSTA) and Register 18-2 shows the Receive Status and Control register (RCSTA). © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 18.1 Asynchronous Operation in Power-Managed Modes ...
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... Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. DS39599G-page 196 R/W-0 U-0 R/W-0 (1) SYNC — BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R-1 R/W-0 TRMT TX9D bit Bit is unknown © 2007 Microchip Technology Inc. ...
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... OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN overrun error bit 0 RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. © 2007 Microchip Technology Inc. PIC18F2220/2320/4220/4320 R/W-0 R/W-0 R-0 CREN ...
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... Bit 1 SYNC — BRGH TRMT CREN ADDEN FERR OERR BRGH = 1 (High Speed) /( 1)) OSC N/A Value on Value on Bit 0 all other POR, BOR Resets TX9D 0000 -010 0000 -010 RX9D 0000 000x 0000 000x 0000 0000 0000 0000 © 2007 Microchip Technology Inc. ...