PIC18F87J50-I/PT Microchip Technology, PIC18F87J50-I/PT Datasheet - Page 344

• Manufacturer Part Number: PIC18F87J50-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J50-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 66
• Number Of Timers: 5
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J50 FAMILY
23.7
When a comparator is active and the device is placed
in Sleep mode, the comparator remains active and the
interrupt is functional, if enabled. This interrupt will
wake-up the device from Sleep mode, when enabled.
Each operational comparator will consume additional
current. To minimize power consumption while in Sleep
mode, turn off the comparators (CON = 0) before
entering Sleep. If the device wakes up from Sleep, the
contents of the CMxCON register are not affected.
TABLE 23-3:
DS39775C-page 344
INTCON
PIR2
PIE2
IPR2
CMxCON
CVRCON
CMSTAT
ANCON1
ANCON0
PORTA
TRISA
LATA
PORTC
LATC
TRISC
PORTF
LATF
TRISF
PORTH
TRISH
Legend:
Note 1:
Name
2:
(2)
(2)
Comparator Operation
During Sleep
(1)
(1)
(1)
Configuration SFR, overlaps with default SFR at this address; available only when WDTCON<4> = 1.
This register is not implemented on 64-pin devices.
— = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
GIE/GIEH PEIE/GIEL
PCFG15
OSCFIF
OSCFIE
OSCFIP
CVREN
TRISC7
TRISH7
TRISF7
PCFG7
LATC7
LATF7
Bit 7
CON
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
RC7
RH7
RF7
—
—
—
—
PCFG14
CVROE
TRISC6
TRISH6
TRISF6
CM2IE
CM2IP
CM2IF
LATC6
LATF6
Bit 6
COE
RC6
RH6
RF6
—
—
—
—
—
PCFG13
TMR0IE
TRISC5
TRISH5
TRISA5
TRISF5
CM1IF
CM1IE
CM1IP
LATC5
LATA5
LATF5
CPOL
CVRR
Bit 5
RA5
RC5
RH5
RF5
—
—
EVPOL1
PCFG12
TRISC4
TRISH4
CVRSS
TRISA4
TRISF4
PCFG4
INT0IE
USBIE
USBIP
LATC4
USBIF
LATA4
LATF4
Bit 4
RA4
RC4
RH4
RF4
—
23.8
A device Reset forces the CMxCON registers to their
Reset state. This forces both comparators and the
voltage reference to the OFF state.
EVPOL0
PCFG11
TRISC3
TRISH3
BCL1IF
BCL1IE
BCL1IP
TRISA3
TRISF3
PCFG3
LATC3
LATA3
LATF3
CVR3
RBIE
Bit 3
RA3
RC3
RH3
RF3
—
Effects of a Reset
PCFG10
TMR0IF
TRISC2
TRISH2
TRISA2
TRISF2
PCFG2
LATC2
LATA2
LATF2
LVDIF
LVDIE
LVDIP
CREF
CVR2
RFC2
Bit 2
RA2
RH2
RF2
—
TMR3IE
TMR3IP
TMR3IF
TRISC1
TRISH1
COUT2
TRISA1
PCFG1
© 2009 Microchip Technology Inc.
INT0IF
LATC1
LATA1
CCH1
CVR1
RFC1
Bit 1
RA1
RH1
—
—
—
—
CCP2IF
CCP2IE
CCP2IP
TRISC0
TRISH0
COUT1
PCFG0
LATC0
LATA0
CCH0
CVR0
RFC0
RBIF
Bit 0
RH0
—
—
—
—
—
—
on Page:
Values
Reset
62
65
65
63
65
61
64
64
64
63
65
64
64
64
64
65
64
64
65
64