PIC18F87J50-I/PT Microchip Technology, PIC18F87J50-I/PT Datasheet - Page 156

• Manufacturer Part Number: PIC18F87J50-I/PT
• Description: IC PIC MCU FLASH 64KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F87J50-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 128KB (64K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 65
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: I2C, MSSP, SPI, EUSART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 66
• Number Of Timers: 5
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DM183022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162087 - HEADER MPLAB ICD2 18F87J50 68/84MA180021 - MODULE PLUG-IN 18F87J50 FS USBAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F87J50 FAMILY
TABLE 10-14: PORTF FUNCTIONS
DS39775C-page 156
RF2/PMA5/
AN7/C2INB
RF3/D-
RF4/D+
RF5/PMD2/
AN10/C1INB/
CV
RF6/PMD1/
AN11/C1INA
RF7/PMD0/
SS1/C1OUT
Legend:
Note 1:
Pin Name
REF
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
XVCR = USB Transceiver, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate PMP configuration when the PMPMX Configuration bit = 0; available on 80-pin devices only.
Function
PMD2
PMD1
PMD0
C1OUT
C2INB
C1INB
CV
C1INA
PMA5
AN10
AN11
AN7
RF2
RF3
RF4
RF5
RF6
RF7
SS1
D+
D-
REF
(1)
(1)
(1)
Setting
TRIS
0
1
x
1
x
1
1
0
1
x
x
1
x
x
0
1
x
x
1
x
0
1
x
x
1
x
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
XVCR
XVCR
XVCR
XVCR
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
DIG
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
LATF<2> data output; not affected by analog input.
PORTF<2> data input; disabled when analog input enabled.
Parallel Master Port address.
A/D input channel 7. Default configuration on POR.
Comparator 2 input B.
PORTF<3> data input; disabled when analog input enabled.
USB bus differential minus line output (internal transceiver).
USB bus differential minus line input (internal transceiver).
PORTF<4> data input; disabled when analog input enabled.
USB bus differential plus line output (internal transceiver).
USB bus differential plus line input (internal transceiver).
LATF<5> data output; not affected by analog input. Disabled when
CV
PORTF<5> data input; disabled when analog input enabled. Disabled
when CV
Parallel Master Port data out.
Parallel Master Port data input.
A/D input channel 10 and Comparator C1+ input. Default input
configuration on POR.
Comparator 1 input B.
Comparator voltage reference output. Enabling this feature disables
digital I/O.
LATF<6> data output; not affected by analog input.
PORTF<6> data input; disabled when analog input enabled.
Parallel Master Port data out.
Parallel Master Port data input.
A/D input channel 11 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
Comparator 1 input A.
LATF<7> data output.
PORTF<7> data input.
Parallel Master Port data out.
Parallel Master Port data input.
Slave select input for MSSP1.
Comparator 1 output.
REF
output enabled.
REF
output enabled.
Description
© 2009 Microchip Technology Inc.