ATMEGA8L-8MU Atmel, ATMEGA8L-8MU Datasheet - Page 99

• Manufacturer Part Number: ATMEGA8L-8MU
• Description: IC AVR MCU 8K 8MHZ 3V 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Package: 32MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 23
• Interface Type: SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer/Counter 1 –
TCNT1H and TCNT1L
Output Compare
Register 1 A –
OCR1AH and OCR1AL
Output Compare
Register 1 B –
OCR1BH and OCR1BL
2486Z–AVR–02/11
Table 40. Clock Select Bit Description
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and Low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers.
Registers” on page 77.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a Com-
pare Match between TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the Compare Match on the following timer clock
for all compare units.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
CS12
0
0
0
0
1
1
1
1
CS11
0
0
1
1
0
0
1
1
R/W
R/W
R/W
7
0
7
0
7
0
CS10
0
1
0
1
0
1
0
1
R/W
R/W
R/W
6
0
6
0
6
0
Description
No clock source. (Timer/Counter stopped)
clk
clk
clk
clk
clk
External clock source on T1 pin. Clock on falling edge
External clock source on T1 pin. Clock on rising edge
R/W
R/W
R/W
I/O
I/O
I/O
I/O
I/O
5
0
5
0
5
0
/1 (No prescaling)
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
R/W
R/W
R/W
OCR1A[15:8]
OCR1B[15:8]
4
TCNT1[15:8]
0
4
0
4
0
OCR1A[7:0]
OCR1B[7:0]
TCNT1[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R/W
R/W
ATmega8(L)
0
0
0
0
0
0
See “Accessing 16-bit
OCR1AH
OCR1BH
OCR1AL
OCR1BL
TCNT1H
TCNT1L
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