ATMEGA8L-8MU Atmel, ATMEGA8L-8MU Datasheet - Page 238

• Manufacturer Part Number: ATMEGA8L-8MU
• Description: IC AVR MCU 8K 8MHZ 3V 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Package: 32MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 23
• Interface Type: SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Two-wire Serial Interface Characteristics
Table 101
Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to
Table 101. Two-wire Serial Bus Requirements
Notes:
238
Symbol
V
V
V
V
t
t
t
I
C
f
Rp
t
t
t
t
t
t
t
t
r
of
SP
i
SCL
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
SU;STO
BUF
(1)
OL
IL
IH
hys
i
(1)
(1)
(1)
(1)
(1)
1. In ATmega8, this parameter is characterized and not 100% tested
2. Required only for f
3. C
4. f
ATmega8(L)
describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega8 Two-wire Serial
Parameter
Input Low-voltage
Input High-voltage
Hysteresis of Schmitt Trigger Inputs
Output Low-voltage
Rise Time for both SDA and SCL
Output Fall Time from V
Spikes Suppressed by Input Filter
Input Current each I/O Pin
Capacitance for each I/O Pin
SCL Clock Frequency
Value of Pull-up resistor
Hold Time (repeated) START Condition
Low Period of the SCL Clock
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time
Data setup time
Setup time for STOP condition
Bus free time between a STOP and START
condition
CK
b
= capacitance of one bus line in pF
= CPU clock frequency
Figure 115 on page
SCL
> 100kHz
IHmin
to V
ILmax
239.
f
CK
(4)
10pF < C
0.1V
> max(16f
3mA sink Current
f
f
SCL
SCL
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
SCL
CC
Condition
≤ 100kHz
> 100kHz
< V
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
≤ 100kHz
> 100kHz
b
< 400pF
SCL
i
< 0.9V
, 250kHz)
(6)
(7)
CC
(3)
(5)
20 + 0.1C
20 + 0.1C
V
----------------------------
V
----------------------------
0.05V
CC
CC
0.7V
3mA
3mA
-0.5
250
100
Min
-10
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
4.0
0.6
4.7
1.3
–
–
0
0
–
0
0
0
0.4V
0.4V
CC
CC
b
b
(2)
(3)(2)
(3)(2)
V
1000ns
------------------ -
0.3V
CC
300ns
--------------- -
50
3.45
Max
300
250
400
0.4
0.9
C
10
10
C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ 0.5
(2)
b
b
CC
2486Z–AVR–02/11
Units
kHz
µA
pF
ns
µs
ns
µs
Ω
V