ATMEGA8L-8MU Atmel, ATMEGA8L-8MU Datasheet - Page 226

• Manufacturer Part Number: ATMEGA8L-8MU
• Description: IC AVR MCU 8K 8MHZ 3V 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Package: 32MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 23
• Interface Type: SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programming the
Fuse High Bits
Programming the Lock
Bits
Reading the Fuse and
Lock Bits
226
ATmega8(L)
The algorithm for programming the Fuse high bits is as follows (refer to
on page 222
1. A: Load Command “0100 0000”
2. C: Load Data Low byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit
3. Set BS1 to “1” and BS2 to “0”. This selects high data byte
4. Give WR a negative pulse and wait for RDY/BSY to go high
5. Set BS1 to “0”. This selects low data byte
The algorithm for programming the Lock Bits is as follows (refer to
page 222
1. A: Load Command “0010 0000”
2. C: Load Data Low byte. Bit n = “0” programs the Lock bit
3. Give WR a negative pulse and wait for RDY/BSY to go high
The Lock Bits can only be cleared by executing Chip Erase.
The algorithm for reading the Fuse and Lock Bits is as follows (refer to
on page 222
1. A: Load Command “0000 0100”
2. Set OE to “0”, BS2 to “0”, and BS1 to “0”. The status of the Fuse Low bits can now be
3. Set OE to “0”, BS2 to “1”, and BS1 to “1”. The status of the Fuse High bits can now be
4. Set OE to “0”, BS2 to “0”, and BS1 to “1”. The status of the Lock Bits can now be read at
5. Set OE to “1”
Figure 108. Mapping Between BS1, BS2 and the Fuse- and Lock Bits During Read
read at DATA (“0” means programmed)
read at DATA (“0” means programmed)
DATA (“0” means programmed)
for details on Command and Data loading):
for details on Command and Data loading):
for details on Command loading):
Fuse low byte
Fuse high byte
Lock bits
BS2
0
1
BS1
0
1
“Programming the Flash” on
DATA
“Programming the Flash”
“Programming the Flash”
2486Z–AVR–02/11