ATMEGA8L-8MU Atmel, ATMEGA8L-8MU Datasheet - Page 231

• Manufacturer Part Number: ATMEGA8L-8MU
• Description: IC AVR MCU 8K 8MHZ 3V 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Package: 32MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 23
• Interface Type: SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Programming
Algorithm
Data Polling Flash
2486Z–AVR–02/11
When writing serial data to the ATmega8, data is clocked on the rising edge of SCK.
When reading data from the ATmega8, data is clocked on the falling edge of SCK. See
113 on page 232
To program and verify the ATmega8 in the Serial Programming mode, the following sequence is
recommended (see four byte instruction formats in
1. Power-up sequence:
2. Wait for at least 20ms and enable Serial Programming by sending the Programming
3. The Serial Programming instructions will not work if the communication is out of synchro-
4. The Flash is programmed one page at a time. The page size is found in
5. The EEPROM array is programmed one byte at a time by supplying the address and data
6. Any memory location can be verified by using the Read instruction which returns the con-
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
When a page is being programmed into the Flash, reading an address location within the page
being programmed will give the value 0xFF. At the time the device is ready for a new page, the
programmed value will read correctly. This is used to determine when the next page can be writ-
ten. Note that the entire page is written simultaneously and any address within the page can be
used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming
this value, the user will have to wait for at least t
a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to
contain 0xFF, can be skipped. See
Apply power between V
tems, the programmer can not guarantee that SCK is held low during Power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”
Enable serial instruction to pin MOSI
nization. When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command
page
address and data together with the Load Program memory Page instruction. To ensure
correct loading of the page, the data Low byte must be loaded before data High byte is
applied for a given address. The Program memory Page is stored by loading the Write
Program memory Page instruction with the 7MSB of the address. If polling is not used,
the user must wait at least t
232).
Note: If other commands than polling (read) are applied before any write operation (FLASH,
EEPROM, Lock Bits, Fuses) is completed, it may result in incorrect programming
together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling is not used, the user must wait
at least t
erased device, no 0xFFs in the data file(s) need to be programmed
tent at the selected address at serial output MISO
operation
Set RESET to “1”
Turn V
218. The memory page is loaded one byte at a time by supplying the 5 LSB of the
CC
WD_EEPROM
power off
for timing details.
before issuing the next byte (see
CC
and GND while RESET and SCK are set to “0”. In some sys-
WD_FLASH
Table 97 on page 232
before issuing the next page (see
WD_FLASH
Table 98 on page
before programming the next page. As
for t
Table 97 on page
WD_FLASH
233):
value.
ATmega8(L)
Table 97 on page
232). In a chip
Table 89 on
Figure
231