ATMEGA8L-8MU Atmel, ATMEGA8L-8MU Datasheet - Page 12

• Manufacturer Part Number: ATMEGA8L-8MU
• Description: IC AVR MCU 8K 8MHZ 3V 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Package: 32MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 23
• Interface Type: SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Purpose
Register File
12
ATmega8(L)
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the
Set
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the
Description” for detailed information.
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
•
•
•
•
Figure 3
Figure 3. AVR CPU General Purpose Working Registers
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-pointer, Y-pointer, and Z-pointer Registers can be set to index any register in
the file.
Description” for detailed information.
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
shows the structure of the 32 general purpose working registers in the CPU.
Registers
Purpose
Working
General
Figure
3, each register is also assigned a Data memory address, mapping them
7
R13
R14
R15
R16
R17
R26
R27
R28
R29
R30
R31
R0
R1
R2
…
…
0
Addr.
0x0D
0x0E
0x0F
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x00
0x01
0x02
0x10
0x11
X-register High Byte
Y-register High Byte
Z-register High Byte
X-register Low Byte
Y-register Low Byte
Z-register Low Byte
“Instruction Set
2486Z–AVR–02/11
“Instruction