ATMEGA8L-8MU Atmel, ATMEGA8L-8MU Datasheet - Page 199

• Manufacturer Part Number: ATMEGA8L-8MU
• Description: IC AVR MCU 8K 8MHZ 3V 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Package: 32MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 23
• Interface Type: SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADC Conversion
Result
ADC Multiplexer
Selection Register –
ADMUX
2486Z–AVR–02/11
After the conversion is complete (ADIF is high), the conversion result can be found in the ADC
Result Registers (ADCL, ADCH).
For single ended conversion, the result is:
where V
Table 74
voltage minus one LSB.
• Bit 7:6 – REFS1:0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in
changed during a conversion, the change will not go in effect until this conversion is complete
(ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external
reference voltage is being applied to the AREF pin.
Table 74. Voltage Reference Selections for ADC
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-
sions. For a complete description of this bit, see
page
• Bits 3:0 – MUX3:0: Analog Channel Selection Bits
The value of these bits selects which analog inputs are connected to the ADC. See
details. If these bits are changed during a conversion, the change will not go in effect until this
conversion is complete (ADIF in ADCSRA is set).
Table 75. Input Channel Selections
Bit
Read/Write
Initial Value
MUX3..0
0000
0001
0010
0011
0100
0101
REFS1
0
0
1
1
201.
IN
and
is the voltage on the selected input pin and V
REFS0
Table
REFS1
0
1
0
1
R/W
7
0
75). 0x000 represents ground, and 0x3FF represents the selected reference
Voltage Reference Selection
AREF, Internal V
AV
Reserved
Internal 2.56V Voltage Reference with external capacitor at AREF pin
REFS0
R/W
CC
6
0
with external capacitor at AREF pin
ADLAR
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
Single Ended Input
R/W
5
0
ref
ADC
turned off
R
4
–
0
=
V
--------------------------
IN
MUX3
R/W
“The ADC Data Register – ADCL and ADCH” on
V
3
0
⋅
REF
1024
MUX2
R/W
REF
2
0
the selected voltage reference (see
MUX1
R/W
1
0
Table
MUX0
R/W
ATmega8(L)
0
0
74. If these bits are
ADMUX
Table 75
199
for