M5307C3 Freescale Semiconductor, M5307C3 Datasheet - Page 73

• Manufacturer Part Number: M5307C3
• Description: KIT EVALUATION FOR MCF5307
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: Microprocessorr

Specifications of M5307C3

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MCF5307
• Interface Type: Ethernet
• For Use With/related Products: MCF5307
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.1.2.
The reset logic provides system initialization. The reset occurs during power-
on and asserts the signal -RSTI which causes total system reset. The reset is
also triggered by the red reset switch and resets the entire processor.
U5 is used to produce active low power-on
ispLSI2032. The reset switch is fed into U4 which generates a signal into U5
which then drive U9's input for reset The U9 device
(-CF_RSTI) and Ethernet RESET (ETH_RST)signals.
ROM
during the initialization.
Vector Base Register, VBR, points to the Flash.
exception table is made at address $00000000 in the SDRAM.
The Software Watchdog
timers are placed in a stop condition. Interrupt controller registers are
initialized with unique interrupt level/priority pairs. The parallel I/O port is
configured for I/O.
3.1.3.
The -HIZ signal is actively driven by the LSI2032 (U9). This Signal is available
for monitor on connector LA3 and J5. This signal should not be driven by the
user.
3.1.4.
The M5307C3 uses a 45MHZ oscillator (U22) to provide the clock
the processor. In addition to U22, there also exist a 20MHz
which feeds into the Ethernet chip. The bus clock out of the MCF5307
clock buffer chip (U18) which is fed into the edge select pin of the MCF5307,
the ispLSI2032 for Ethernet timing (1/4 bus clock), SRAM
(U23).
3.1.5.
Monitor performs the following configurations of internal resources
The -HIZ Signal
The
Watchdog
The Reset Logic
Clock
Timer
Freescale Semiconductor, Inc.
Circuitry
For More Information On This Product,
Timer is disabled, Bus Monitor enabled, and internal
The instruction cache is
Go to: www.freescale.com
49
RESET signal which feeds into the
invalidated and disabled. The
generates the system reset
However,
(U19), and SDRAM
a copy of the
to CLKIN pin of
oscillator (U6)
drives a