M5307C3 Freescale Semiconductor, M5307C3 Datasheet - Page 128

• Manufacturer Part Number: M5307C3
• Description: KIT EVALUATION FOR MCF5307
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: Microprocessorr

Specifications of M5307C3

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MCF5307
• Interface Type: Ethernet
• For Use With/related Products: MCF5307
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

For SDRAM to MCF5307 hold time the following calculation was used:
Thus, this analysis indicates all timing has adequate margin, even for PC66 memory, as long as a zero-delay
clock driver is used. Although this timing analysis example is for a PC66 memory, there are no timing
violations when using PC100 memory either.
1.5 Timing Considerations for Older OH55J Mask
The timing analysis reviewed in the previous section applies to the most recent MCF5307 mask, the 00J20C.
For those using the 0H55J mask of the MCF5307, the output hold time (parameter B11, and parameter
B11a), have different values from the 0H55J mask. Specifically, the output hold time for address, data and
normal bus control signals is 0.0 nS, and for DRAM control lines such as RAS and CAS, the hold time is -
1.0 nS.
Thus, for write cycles, the subtracting a 1.5 nS PC66 input hold time from a -1.5 nS MCF5307 output hold
time results in a -3 nS timing margin for SDRAM signals (-2.5 nS for PC100 memory).
In other words, there is insufficient hold time. The proposed solution is to use a clock driver that can provide
a 1.0 nS negative propagation delay. This is actually possible with the zero-delay buffers from Cypress. The
reference output can be loaded with a 20 pF capacitor, yielding a positive setup time in advance of the clock
output. The following is the resultant analysis for all important times.
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- 2 nS (Input hold time for MCF5307) (Parameter B4)
= 1 nS timing margin
-11 nS (BCLKO to Valid Output time)
- 2 nS (PC100 Memory Setup time)
- 1 nS (Clock Driver Advance)
= 8 nS timing margin
- 5 nS MUX PLD max. propagation delay
=
- 1 nS (worst case Output hold time MCF5307 for SDRAM controls)
+ 1 nS (advance from clock driver)
+ 1 nS (1 nS skew from termination resistors
- 1 nS (input hold time for PC100 Memory)
=
MCF5307-to-SDRAM setup time:
MCF5307-to-SDRAM hold time for writes:
The OH55J mask set MCF5307 Errata published hold time from clock rising edge is 0.0 nS
(Parameter B11) for normal signals and –1.0 nS for SDRAM control signals. Given the additional
1 nS advance on the clock with the loaded reference signal, this leaves a 1.0 nS hold time for normal
3 nS (Output hold time for PC66 and PC100 memory)
22 nS (Bus Frequency)
3 nS worst case timing margin
0 nS timing margin
Connecting the MCF5307 to 168-Pin Unbuffered SDRAM DIMMs
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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