C8051F310-TB Silicon Laboratories Inc, C8051F310-TB Datasheet - Page 90
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C8051F310-TB
Manufacturer Part Number
C8051F310-TB
Description
BOARD PROTOTYPING W/C8051F310
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F310-TB
Contents
Board
Processor To Be Evaluated
C8051F31x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F310
Silicon Family Name
C8051F31x
Kit Contents
Board
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F310
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F310/1/2/3/4/5/6/7
8.2.7. Register Descriptions
Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits
should not be set to logic 1. Future product versions may use these bits to implement new features in
which case the reset value of the bit will be logic 0, selecting the feature's default state. Detailed descrip-
tions of the remaining SFRs are included in the sections of the data sheet associated with their corre-
sponding system function.
90
Register
TMR2L
TMR2RLH
TMR2RLL
TMR3CN
TMR3H
TMR3L
TMR3RLH
TMR3RLL
VDM0CN
XBR1
XBR0
0x84-0x86, 0x96-0x97,
0xAB-0xAF, 0xB4, 0xB9,
0xBF, 0xC7, 0xC9, 0xCE,
0xCF, 0xD2, 0xD3, 0xD7,
0xDF, 0xE3, 0xE5, 0xF5
Bits7–0: DPL: Data Pointer Low.
R/W
Bit7
The DPL register is the low byte of the 16-bit DPTR. DPTR is used to access indirectly
addressed Flash memory.
R/W
Bit6
Address
0xCC
0xCB
0xCA
0x91
0x95
0x94
0x93
0x92
0xFF
0xE2
0xE1
Table 8.3. Special Function Registers (Continued)
SFR Definition 8.1. DPL: Data Pointer Low Byte
R/W
Bit5
Description
Timer/Counter 2 Low
Timer/Counter 2 Reload High
Timer/Counter 2 Reload Low
Timer/Counter 3Control
Timer/Counter 3 High
Timer/Counter 3Low
Timer/Counter 3 Reload High
Timer/Counter 3 Reload Low
V
Port I/O Crossbar Control 1
Port I/O Crossbar Control 0
Reserved
DD
Monitor Control
R/W
Bit4
Rev. 1.7
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
SFR Address:
00000000
Reset Value
0x82
Page
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