C8051F350DK Silicon Laboratories Inc, C8051F350DK Datasheet - Page 140

• Manufacturer Part Number: C8051F350DK
• Description: DEV KIT FOR F350/351/352/353
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F350DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F35x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F350
• Silicon Family Name: C8051F35x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F350, 351, 352, 353
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1083

C8051F350/1/2/3
Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note
that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and
SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).
UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART
RX0 is always assigned to P0.5. Comparator outputs are also fixed: CP0A will appear only on P1.4, CP0
will appear only on P1.5. Standard Port I/Os appear contiguously after the prioritized functions have been
assigned.
Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the
NSSMD1–NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not
be routed to a Port pin.
140
SF Signals
PIN I/O
TX0
RX0
CP0A
CP0
SCK
MISO
MOSI
NSS*
SDA
SCL
/SYSCLK
CEX0
CEX1
CEX2
ECI
T0
T1
SF Signals
Figure 18.4. Crossbar Priority Decoder with Crystal Pins Skipped
Port pin potentially assignable to peripheral
Special Function Signals are not assigned by the crossbar.
When these signals are enabled, the CrossBar must be
manually configured to skip their corresponding port pins.
0
0
1
0
x1
2
1
P0SKIP[0:7]
x2
3
1
P0
4
0
5
0
CNVSTR
6
0
Rev. 1.1
7
0
(*4-Wire SPI Only)
0
0
1
0
2
0
P1SKIP[0:7]
3
0
P1
4
0
5
0
IDA0 IDA1
6
0
7
0
P2
0