C8051F350DK Silicon Laboratories Inc, C8051F350DK Datasheet - Page 116

• Manufacturer Part Number: C8051F350DK
• Description: DEV KIT FOR F350/351/352/353
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F350DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F35x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F350
• Silicon Family Name: C8051F35x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F350, 351, 352, 353
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1083

C8051F350/1/2/3
14.1. Power-On Reset
During power-up, the device is held in a reset state and the /RST pin is driven low until V
V
ramp time increases (V
plots the power-on and V
delay (T
Note: The maximum V
reset before V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset. The V
a power-on reset.
116
RST
. An additional delay occurs before the device is released from reset; the delay decreases as the V
PORDelay
DD
) is typically less than 0.3 ms.
Logic HIGH
Logic LOW
reaches the V
Figure 14.2. Power-On and
2.70
2.55
2.0
1.0
DD
DD
DD
ramp time is 1 ms; slower ramp times may cause the device to be released from
ramp time is defined as how fast V
/RST
monitor reset timing. For valid ramp times (less than 1 ms), the power-on reset
RST
V
RST
level.
Power-On
Reset
T
PORDelay
Rev. 1.1
V
DD
Monitor Reset Timing
DD
ramps from 0 V to V
Monitor
Reset
VDD
DD
monitor is enabled following
VDD
RST
DD
t
). Figure 14.2.
settles above
DD