C8051F350DK Silicon Laboratories Inc, C8051F350DK Datasheet - Page 117
![DEV KIT FOR F350/351/352/353](/photos/9/23/92327/c8051f350dk_sml.jpg)
C8051F350DK
Manufacturer Part Number
C8051F350DK
Description
DEV KIT FOR F350/351/352/353
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F350DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F35x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F350
Silicon Family Name
C8051F35x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F350, 351, 352, 353
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1083
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F350DK
Manufacturer:
SiliconL
Quantity:
8
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14.2. Power-Fail Reset /
When a power-down transition or power irregularity causes V
monitor will drive the /RST pin low and hold the CIP-51 in a reset state (see Figure 14.2). When V
returns to a level above V
nal data memory contents are not altered by the power-fail reset, it is impossible to determine if V
dropped below the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be
valid. The V
defined state (enabled/disabled) is not altered by any other reset source. For example, if the V
is disabled by software, and a software reset is performed, the V
reset. To protect the integrity of Flash contents, it is strongly recommended that the V
remain enabled and selected as a reset source if software contains routines which erase or write
Flash memory.
The V
reset source before it is enabled and stabilized may cause a system reset. The procedure for re-enabling
the V
See Figure 14.2 for V
See Table 14.1 for complete electrical characteristics of the V
Bit7:
Bit6:
Bits5–0: Reserved. Read = Variable. Write = don’t care.
VDMEN
DD
R/W
DD
Bit7
Step 1. Enable the V
Step 2. Wait for the V
Step 3. Select the V
monitor and configuring the V
monitor must be enabled before it is selected as a reset source. Selecting the V
VDMEN: V
This bit is turns the V
resets until it is also selected as a reset source in register RSTSRC (SFR Definition 14.2).
The V
ing the V
reset. See Table 14.1 for the minimum V
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
DD
DD
V
DD
DD
DD
DD
DD
monitor is enabled and selected as a reset source after power-on resets; however its
Note: This delay should be omitted if software contains routines which erase or
write Flash memory.
STAT: V
Bit6
DD
R
STAT Reserved Reserved Reserved Reserved Reserved Reserved
Monitor Disabled.
Monitor Enabled (default).
is at or below the V
is above the V
SFR Definition 14.1. VDM0CN:
DD
Monitor must be allowed to stabilize before it is selected as a reset source. Select-
DD
DD
monitor timing; note that the reset delay is not incurred after a V
DD
monitor as a reset source before it has stabilized may generate a system
RST
Monitor Enable.
Status.
DD
, the CIP-51 will be released from the reset state. Note that even though inter-
Bit5
DD
R
DD
monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
V
monitor (VDMEN bit in VDM0CN = ‘1’).
monitor to stabilize (see Table 14.1 for the V
DD
DD
DD
monitor circuit on/off. The V
monitor threshold.
Monitor
DD
DD
Bit4
R
monitor as a reset source is shown below:
monitor threshold.
Rev. 1.1
Bit3
R
DD
Monitor turn-on time.
V
DD
DD
Bit2
DD
R
DD
DD
monitor.
Monitor Control
DD
to drop below V
Monitor output).
Monitor cannot generate system
monitor will still be disabled after the
C8051F350/1/2/3
Bit1
R
DD
Monitor turn-on time).
SFR Address:
RST
Bit0
R
, the power supply
DD
DD
monitor reset.
0xFF
monitor as a
Reset Value
DD
Variable
DD
monitor
monitor
117
DD
DD
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