ADM1041-EVAL Analog Devices Inc, ADM1041-EVAL Datasheet - Page 47

• Manufacturer Part Number: ADM1041-EVAL
• Description: BOARD EVALUATION ADM1041
• Manufacturer: Analog Devices Inc

Specifications of ADM1041-EVAL

• Main Purpose: AC/DC, Secondary Side
• Outputs And Type: 1, Non-Isolated
• Power - Output: 24W
• Voltage - Output: 12V
• Current - Output: 2A
• Voltage - Input: 85 ~ 132VAC
• Board Type: Fully Populated
• Utilized Ic / Part: ADM1041
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Frequency - Switching: -
• Regulator Topology: -
• Lead Free Status / Rohs Status: Not Compliant

Bit No.
3–2
1
0
Table 26. Register 11h, Config5. Power-On Default from EEPROM Register 8111h 8110h during Power-Up.
Bit No.
7
6
5
4–3
2
1
0
Table 27. Register 12h, Config6. Power-On Default from EEPROM Register 8112h 8110h during Power-Up.
Bit No.
7
6
5
4–3
2
1
0
Table 28. Register 13h, Config7. Power-On Default from EEPROM Register 8113h during Power-Up.
Bit No.
Name
ssrs1, ssrs0
add1
trim_lock
Name
curr_lim_dis
polpen0
polcbd0
Reserved
ocpts2
gndok_dis
cbdlm
Name
rsm
up_AC_OK_m
m_acsns_w
ocpts1, ocpts0
acss
m_pson_w
I
Name
SHARE
_clamp
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
(W)
R/W
(W)
(W)
R/W
R/W
R/W
R/W
R/W
X
R/W
R/W
R/W
Description
Description
Restart Mode. When rsm = 1, the circuit attempts to restart the supply after an undervoltage or
overcurrent at about 1 second intervals.
Latch Mode. When rsm = 0, UV and OC faults latch the output off. Cycling PSON or removing the
supply to the IC is then required to reset the latch and permit a restart.
Configure microprocessor to control/gate signal from acinok to acsok.
0 = standalone.
1 = microprocessor support mode.
Microcessor control of acsok (AC
OCP Ridethrough (Reg 11h[2] = 0)
b4
0
0
1
1
AC Sense Mode. 0 means AC_OK is derived from AC
AC
Microprocessor control of pson.
0 = 75%. Set current share clamp release threshold.
1 = 88%.
Description
0
1
1
Soft-Start Step
b3
0
0
1
1
EEPROM programmable second address bit.
When this bit is set, the trim registers including this register are not writable via SMBus. To
make registers writable again, the trim-lock bit in the EEPROM must first be erased and the
value downloaded using either power-up or test download.
Description
Mask effect of OCP to general logic (status flag still gets asserted) when curr_lim_dis = 1.
Sets polarity of PEN output. Refer to the Configuration table (Table 45).
Sets polarity of CBD output. Refer to the Configuration table (Table 45).
Don’t Care.
Set this bit to 1 when 0 OCP ridethrough is required. A small delay still exists. Refer to Reg 12h
and the Configuration table (Table 45).
Disable gndok input to power management debounce logic.
Select CBD latch mode. 0 = nonlatching; 1 = latching.
SENSE
2.
b3
0
1
0
1
Rev. A | Page 47 of 64
1
0
1
b2
0
1
0
1
Period
1 second
2 seconds
3 seconds
4 seconds
2%
3%
4%
Rise Time
300 µs
10 ms
20 ms
40 ms
SENSE
).
OCP Ridethrough (Reg11h[2] = 1)
b4
0
0
1
1
SENSE
1, whereas 1 means AC_OK is derived from
b3
0
1
0
1
Period
128 µs
256 µs
384 µs
512 µs
ADM1041