ADM1041-EVAL Analog Devices Inc, ADM1041-EVAL Datasheet - Page 12

• Manufacturer Part Number: ADM1041-EVAL
• Description: BOARD EVALUATION ADM1041
• Manufacturer: Analog Devices Inc

Specifications of ADM1041-EVAL

• Main Purpose: AC/DC, Secondary Side
• Outputs And Type: 1, Non-Isolated
• Power - Output: 24W
• Voltage - Output: 12V
• Current - Output: 2A
• Voltage - Input: 85 ~ 132VAC
• Board Type: Fully Populated
• Utilized Ic / Part: ADM1041
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Frequency - Switching: -
• Regulator Topology: -
• Lead Free Status / Rohs Status: Not Compliant

ADM1041
1
2
3
4
5
6
7
8
9
10
This specification is a measure of I
erase.
Specification is not production tested, but is supported by characterization data at initial product release.
Four external divider resistors are the same ration, which is selected to produce 2.0 V nominal at Pin 21 while at zero load current. Recommended values are
Chopper off.
The maximum specification here is the maximum source current of Pin 8 as specified by the Absolute Maximum Ratings.
All internal amplifiers accept inputs with common range from GND to V
These pins can be configured as open-drain N-channel or P-channel, (except PSON) and as normal or inverted logic polarity. Refer to Table 45.
A logic true or false is defined strictly according to the signal name. Low and high refer to the pin or signal voltages.
Endurance is qualified to 100,000 cycles as per JEDEC std. 22 method A117, and measured at −40°C, +25°C, and +85°C. Typical endurance at 25°C is 250,000 cycles.
with junction temperature.
Retention lifetime equivalent at junction temperature (T
R
R
TOP
BOTTOM
SDA
SCL
3.3 V
680R
1K
P
t
BUF
S
5.0 V
1K.5
1K
t
HD:STA
DD
during an EEPROM page erase cycle. The current is a dynamic. Refer to Figure 29 for a typical I
12 V
1K
5K1
t
LOW
t
R
t
HD:DAT
J
) = 55°C as per JEDEC std. 22 method A117. Retention lifetime based on an activation energy of 0.6 V. Derates
Figure 6. Amplifier Inputs and Outputs
Figure 5. Serial Bus Timing Diagram
t
HIGH
t
F
DD
t
Rev. A | Page 12 of 64
SU:DAT
− 2 V. The output is rail to rail but the input is limited to GND to V
SHRO
SHRS+
SHRS–
VA
VB
R1
R1
S
VA = V
VB = V
R1 + R2 ≥ 1kΩ
t
SU:STA
DD
DD
t
– 0.4V
– 2V
HD:STA
DD
t
SU:STO
plot during an EEPROM page
DD
− 2 V. See Figure 6.
P