ADM1041-EVAL Analog Devices Inc, ADM1041-EVAL Datasheet

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ADM1041-EVAL

Manufacturer Part Number
ADM1041-EVAL
Description
BOARD EVALUATION ADM1041
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADM1041-EVAL

Main Purpose
AC/DC, Secondary Side
Outputs And Type
1, Non-Isolated
Power - Output
24W
Voltage - Output
12V
Current - Output
2A
Voltage - Input
85 ~ 132VAC
Board Type
Fully Populated
Utilized Ic / Part
ADM1041
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Frequency - Switching
-
Regulator Topology
-
Lead Free Status / Rohs Status
Not Compliant
PRODUCT FEATURES
Digital calibration via internal EEPROM
Supports SSI specification
Comprehensive fault detection
Reduced component count on secondary side
Standalone or microcontroller control
SECONDARY-SIDE FEATURES
Generates error signal for primary-side PWM
Output voltage adjustment and margining
Current sharing
Current limit adjustment
OrFET control
Programmable soft-start slew rate
Standalone or microcontroller operation
Differential load voltage sense
AC mains undervoltage detection (ac sense)
Overvoltage protection
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
CONTROLLER
PWM
V
DD
ISOLATION BARRIER
V
DD
V
DD
OTP
BIAS
V
DD
THERMISTOR
Figure 1. Typical Application Circuit
RS
C
C
V
CBD
V
ICT
PULSE
MON2
PEN
C
SCMP
GND
S
CMP
S
DD
CMP
ADM1041
–/V
+
INTERFACE AND INTERNAL FEATURES
SMBus interface (I
Low-drift precision 2.5 V reference
Voltage error amplifier
Differential current sense
Sense resistor or current transformer option
Overvoltage protection
Undervoltage protection
Overcurrent protection
Overtemperature protection
Start-up undervoltage blanking
Programmable digital debounce and delays
352-byte EEPROM available for field data
160-byte EEPROM for calibration
Ground continuity monitoring
APPLICATIONS
Network servers
Web servers
Power supply control
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
LS
AC_OK
DC_OK
Current Share and Housekeeping
SHRO
PSON
SHRS
ADD0
V
SDA
SCL
DD
V
V
Secondary-Side Controller with
F
F
S
S
G
D
+
OrFET
2
CONTROLLER
C compatible)
© 2004 Analog Devices, Inc. All rights reserved.
OPTIONAL
MICRO-
SHARE BUS
V
OUT
R
V
LOAD
V
V
GND
S
S
ADM1041
OUT
+
www.analog.com
V
DD

Related parts for ADM1041-EVAL

ADM1041-EVAL Summary of contents

Page 1

... ICT PULSE AC_OK DC_OK MON2 PSON PEN ADD0 C CMP SCMP GND Figure 1. Typical Application Circuit One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 Secondary-Side Controller with ADM1041 2 C compatible) OrFET V R LOAD GND DD SHARE BUS OUT V ...

Page 2

... ADM1041 TABLE OF CONTENTS Specifications..................................................................................... 6 Absolute Maximum Ratings.......................................................... 13 ESD Caution................................................................................ 13 Pin Configuration and Function Descriptions........................... 14 Terminology .................................................................................... 17 Theory of Operation ...................................................................... 19 Power Management.................................................................... 19 Gain Trimming and Configuration ......................................... 19 Differential Remote Sense Amplifier............................................ 20 Set Load Voltage.......................................................................... 20 Load Overvoltage (OV) ............................................................. 20 Local Voltage Sense .................................................................... 20 Local OverVoltage Protection (OVP)...................................... 20 Local UnderVoltage Protection (UVP) ................................... 20 False UV Clamp ...

Page 3

... These three elements are summed together to generate a control signal (V loop via an optocoupler to the primary side PWM controller. Another key feature of the ADM1041 is its control of an OrFET. The OrFET causes lower power dissipation across the ORing diode. The main function of the OrFET is to disconnect the ...

Page 4

... ADM1041 Figure 3. Chip Diagram, Part 1 Rev Page ...

Page 5

... Figure 4. Chip Diagram, Part 2 Rev Page ADM1041 ...

Page 6

... ADM1041 SPECIFICATIONS T = –40 to +85° ± 10%, unless otherwise noted Table 1. Parameter SUPPLIES Current Consumption Peak I during EEPROM Erase Cycle DD, UNDERVOLTAGE LOCKOUT Start-Up Threshold Stop Threshold Hysteresis V , 2.5 V REF REFOUT Output Voltage Line Regulation Load Regulation 2 Temperature Stability Long-Term Stability 2 Current Limit ...

Page 7

... Rev Page ADM1041 Test Conditions/Comments See Figure 9. Set by external resistor divider 1 RANGE 8 bits, 255 steps, Reg 18h[7:0]. See Table 33. V RANGE 8 bits, 255 steps Reg 0Ah[7:0]. See Table 33. V RANGE 8 bits, 255 steps, Reg 09h[7:0]. See Table 18. ...

Page 8

... ADM1041 Parameter DC Offset Trim Range (with respect to input) DC Offset Trim Step Size (with respect to input) CURRENT SENSE CALIBRATION 2 Total Current Sense Error (Gain and Offset) Gain Range (I ) SENSE Gain Setting 1 (Reg 16h[2:0] = 000) Gain Setting 2 (Reg 16h[2:0] = 001) Gain Setting 3 (Reg 16h[2:0] = 010) ...

Page 9

... V 0.4 V 0.8 V −5 +5 µA 0.25 2.0 V – Rev Page ADM1041 Test Conditions/Comments See Figure 13 After I calibration SHARE 2.0 ≤ V ≤ 2.8 V typ. 5 bits, 31 steps. SHARE Reg 04h[7:3]. See Table 13 ±20 µA. See Figure 12. CCMP V = > CCMP V = < V – ...

Page 10

... ADM1041 Parameter Reverse Voltage Detector Turn-Off Threshold Reverse Voltage Detector Turn-On Threshold FD Input Impedance FS Input Impedance AC 1/AC 2 COMPARATOR SENSE SENSE (AC or Bulk Sense) Threshold Voltage Threshold Adjust Range Threshold Trim Step Hysteresis Adjust Range Hysteresis Trim Step Noise Filter PULSE-IN Threshold Voltage ...

Page 11

... Years Rev Page ADM1041 Test Conditions/Comments Reg 0Fh[4:2] = 010 or 100. See Table 24. Reg 0Fh[4:2] = 011 or 101. See Table 24. Reg 0Eh[4:2] = 00x. See Table 23. Reg 0Fh[1:0] = 00. See Table 24. Reg 0Fh[1:0] = 01. See Table 24. Reg 0Fh[1:0] = 10. See Table 24. ...

Page 12

... ADM1041 1 This specification is a measure of I during an EEPROM page erase cycle. The current is a dynamic. Refer to Figure 29 for a typical I DD erase. 2 Specification is not production tested, but is supported by characterization data at initial product release. 3 Four external divider resistors are the same ration, which is selected to produce 2.0 V nominal at Pin 21 while at zero load current. Recommended values are 3 ...

Page 13

... Exposure to absolute maximum rating conditions for extended periods may affect 300°C device reliability 150°C pin). CT Rev Page ADM1041 ...

Page 14

... MON1: When MON1 is selected for this pin, its input is compared against a 1.25 V comparator that could be used for monitoring a post regulated output; includes overvoltage, undervoltage, and overtemperature conditions. V SHRO –/FS SHRS SCMP CMP CMP S ADM1041 TOP VIEW GND REF (Not to Scale) ICT DC_OK/MON4 8 17 PULSE/AC 1/MON1 PSON/MON3 9 16 SENSE AC 2/MON2 ADD0 10 15 SENSE CBD/ALERT SDA/ ...

Page 15

... LINK: In non-microprocessor applications, this pin can be programmed to provide the PSON being left to float. One address bit is available via programming at the DD : This is a 2.5 V precision reference voltage capable of sourcing 2 mA. This function is continuously , an external level shifter is required to drive the higher gate DD Rev Page ADM1041 source must be different from SENSE LINK ON ...

Page 16

... ADM1041 Pin No. Mnemonic Description This pin is the positive remote load voltage sense input and is normally divided down from the power S supply output voltage to 2 load using an external voltage divider. The input impedance is high. 22 SCMP Output of the Current Share Transconductance Error Amplifier. Compensation is a series capacitor and resistor to ground ...

Page 17

... ASIC, the POR function clears all latches and puts DD to prevent spurious modes of operation that might occur below a specific voltage. must be known to the IC, either by virtue of the on-board AC SENSE Rev Page ADM1041 or DD SENSE or communicated by the SENSE is low, UVB is enabled, which SENSE ...

Page 18

... ADM1041 Mnemonic Description Pulse_OK As well as providing ac sense, the preceding connection to the transformer is used to gate the operation of the OrFET circuit. If the output of the transformer is good and has no problems, the OrFET circuit allows gate drive to the OrFET. AC Hysteresis AC Sense Hysteresis. Configurable voltage on the ac sense input allows the ac sense upper and lower threshold to be adjusted to suit different amounts of low frequency ripple present on the bulk capacitor ...

Page 19

... REF REF GAIN TRIMMING AND CONFIGURATION The various gain settings and configurations throughout the ADM1041 are digitally set up via the SMBus after it has been exceeds the DD loaded onto its printed circuit board. There is no need for external trim potentiometers. An initial adjustment process overvoltage, and a should be carried out in a test system ...

Page 20

... ADM1041 DIFFERENTIAL REMOTE SENSE AMPLIFIER This amplifier senses the load voltage and is the main voltage feedback input. A differential input is used to compensate for the voltage drop on the negative output cable of the power supply. An external voltage divider should be designed to set the V + pin to approximately 2.0 V with respect gain is 1 ...

Page 21

... Because the offset compensation circuit itself has some inaccu- racies, the best overall current sense accuracy is obtained by using more closely matched external dividers and then selecting a low compensation range. See Figure 14. Rev Page ADM1041 ...

Page 22

... The share driver amplifier has a total of 100 mV positive offset built into it. In order to use the ADM1041 in CT mode necessary to compensate for this additional 100 mV offset. This is achieved by adding in a positive offset on the CT input. This also allows any negative amplifier offsets in the CT chain to be nulled out ...

Page 23

... Figure 13. Current Sense Rev Page ADM1041 ...

Page 24

... ADM1041 CURRENT SHARE The current share method is the master–slave type, which means that the power supply with the highest output current automatically becomes the master and controls the share bus signal. All other power supplies become slaves, and the share bus signal causes them to increase their output voltages slightly until their output currents are almost equal to that of the master ...

Page 25

... Figure 14. Current Share Circuit and Soft-start Rev Page ADM1041 ...

Page 26

... ADM1041 SHARE 1V OFFSET 100% I OUT Figure 15. Load Share Characteristic Rev Page ...

Page 27

... TO OrFET SOURCE TO CURRENT SENSE RESISTOR AND OrFET GATE 0.525V 9 5.3kΩ 1 SELECT AC SENSE 1. 5.3kΩ TRIM HYSTERESIS Figure 16. Pulse In and AC Sense Circuit Rev Page rather than AC 1. This allows a separate dc SENSE SENSE PULSEOK CLK Q 1 SEC R AC_OK CLK ADM1041 ...

Page 28

... A slightly larger filter capacitor may be used on the voltage divider at Pin 6 to speed up this function. Figure 17 shows the typical response time of the ADM1041 to such an event. In the plot ramped down and the response FD ...

Page 29

... Figure 19. OrFET Turn- Off Time (Inverse Polarity) CURRENT PULSEOK LOADOK REVERSEOK RESET VOLTAGE DETECTOR Figure 20. OrFET Turn-On Time (Inverse Polarity +10V OUT PENOK OrFET OK POLARITY V REF Figure 21. OrFET Gate Drive Circuit Rev Page ADM1041 T = 618ns TOTAL 64 506ns T = 112ns DELAY V OUT SOURCE DRAIN GATE ...

Page 30

... It can be configured as an open-drain N- channel or P-channel MOSFET and as positive or negative (inverted) logic. A pull-up or pull-down resistor is required. This pin may be wire-ORed with the same pin on other ADM1041 ASICs in the power supply. When the DC_OK pin is not used as such, it can be configured as an analog input, MON4. MON4 This is the alternative analog comparator function for the DC_OK pin (Pin 17) ...

Page 31

... It can be configured as an open-drain N-channel or P-channel MOSFET and as positive or negative (inverted) logic. A pull-up or pull-down resistor is required. This pin can be wire-ORed with the same pin on other ADM1041 ASICs in the power supply. When the AC_OK pin is not used as such, it can be configured as an analog input, MON5 voltage reference ...

Page 32

... ADM1041 Figure 24. General Logic Rev Page ...

Page 33

... LINK and can be connected to the same ON pin on other ADM1041s in the power supply fault is detected in any ADM1041, causing it to shut down, it uses this pin to signal the other ADM1041s to also shut down auto- restart has been configured, it also causes all ADM1041s to turn on together. SCL/AC_OKLink ...

Page 34

... SMBus SERIAL INTERFACE Control of the ADM1041 is carried out via the SMBus. The ADM1041 is connected to this bus as a slave device under the control of a master device. The ADM1041 has a 7-bit serial bus slave address. When the device is powered up, it does so with a default serial bus address. ...

Page 35

... ADM1041 FRAME 1 ADDRESS POINTER REGISTER BYTE 1 SCLK (CONTINUED) SDATA (CONTINUED R ACK. BY ADM1041 ADDRESS POINTER REGISTER BYTE Figure 26. Writing to the Address Pointer Register Only R ACK. BY ADM1041 DATA BYTE FROM ADM1041 Figure 27. Reading Data from a Previously Selected Register Rev Page ACK. BY ADM1041 FRAME ...

Page 36

... EEPROM occupies the address locations from 8000h to 813Fh. The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADM1041 are discussed in the next sections. The following abbreviations are used in the diagrams: S—START P—STOP R— ...

Page 37

... SMBus clock for repeated or block write operations. The start address for a block write must have been set previously. In the case of the ADM1041, this is done by a send byte operation to set a RAM address write byte/ word operation to set an EEPROM address. ...

Page 38

... In this operation, the master device reads a block of data from a slave device. The start address for a block read must previously have been set. In the case of the ADM1041, this is done by a send byte operation to set a RAM address write byte/word operation to set an EEPROM address. The block read operation ...

Page 39

... EEPROM memory that starts at 8100h and transfers the contents into the appropriate trim-level and control registers (00h to 1Bh). In this way, the ADM1041 can be preconfigured with the desired operating characteristics without the host system having to download the data over the SMBus ...

Page 40

... ADM1041 EXTENDED SMBus ADDRESSING A potential problem exists when using more than three ADM1041s in a single power supply. The first time the device is powered up, Bit 1 of Configuration Register 1 (ADD1 This means that only three device addresses are initially available defined by ADD0; if there are more than three devices in a system, two or more of them will have duplicate addresses ...

Page 41

... From EEPROM Register 8119h From EEPROM Register 811Ah From EEPROM Register 811Bh 41h—Hardwired by manufacturer Xh—Hardwired by Manufacturer XXh—Depends on status of ADM1041 at power-up. XXh—Depends on status of ADM1041 at power-up. XXh—Depends on status of ADM1041 at power-up. Rev Page ADM1041 Factory EEPROM Value 00h 00h 00h ...

Page 42

... ADM1041 DETAILED REGISTER DESCRIPTIONS Table 9. Register 00h, Status1. Power-On Default XXh (Refer to the logic schematic—Figure 24.) Bit No. Name R/W 7 ovfault R 6 uvfault R 5 ocpto R 4 mfg1 R 3 mfg2 R 2 mfg3 R 1 mfg4 R 0 mfg5 R Table 10. Register 01h, Status2. Power-On Default XXh (Refer to the logic schematic—Figure 24.) Bit No ...

Page 43

... Description Don’t Care Locks 8140h–817Fh Available FRU. Locks 8120h–813Fh ADI cal registers, Locked by manufacturer. Locks 8100h–811Fh ADM1041 Config Boot registers. Locks 80C0h–80FFh Available FRU. Locks 8080h–80BFh Available FRU. Locks 8040h–807Fh Available FRU. Locks 8000h–803Fh Available FRU ...

Page 44

... ADM1041 Table 19. Register 0Ah, Local OVP Trim. Power-On Default from EEPROM Register 810Ah during Power-Up. Bit No. Name R/W 7–0 local_ovp R/W Table 20. Register 0Bh, OTP Trim. Power-On Default from EEPROM Register 810Bh during Power-Up. Bit No. Name R/W 7–4 otp_trim R/W 3–1 ...

Page 45

... iopin > 1. iopin > 1. mfg3 ov uv iopin < 1. iopin > 1. iopin < 1. iopin > 1. iopin < 1. iopin > 1. iopin < 1. iopin > 1. iopin < 1. iopin > 1. iopin < 1. iopin > 1. ADM1041 (true = high) (true = high) (true = low) (true = high) ...

Page 46

... ADM1041 Table 24. Register 0Fh, Config3. Power-On Default from EEPROM Register 810Fh during Power-Up. Bit No. Name R/W 7–5 mn4s2, mn4s1, R/W mn4s0 4–2 mn5s2, mn5s1, R/W mn5s0 1–0 psonts1, psonts0 R/W Table 25. Register 10h, Config4. Power-On Default from EEPROM Register 8110h during Power-Up. ...

Page 47

... AC Sense Mode. 0 means AC_OK is derived from SENSE Microprocessor control of pson 75%. Set current share clamp release threshold 88%. Description Rev Page ADM1041 OCP Ridethrough (Reg11h[ Period 0 0 128 µ 256 µ 384 µ 512 µs 1, whereas 1 means AC_OK is derived from ...

Page 48

... ADM1041 Bit No. Name R/W 7 polpen1 R/W 6 polcbd1 R/W 5 polDC_OK1 R/W 4 polAC_OK1 R/W 3 polfg R/W 2 m_shr_clmp (W) 1 m_cbd_w R/W 0 m_cbd_clr R/W Table 29. Register 14h, Current Sense Divider Error Trim 1. Power-On Default from EEPROM Register 8114h during Power-Up. Bit No. Name R/W 7–0 os_div R/W Table 30 ...

Page 49

... This register contains the false UV clamp settings. Description This register contains the set load voltage trim settings. Description ovfault uvfault ocpto (ridethrough timed out, ocpf flag) acsnsb (inverted) ocpf otp (MON5 OV) orfetokb (inverted) Share_OKb (inverted) Rev Page ADM1041 Range Gain −8 mV −1 −15 mV −2 −30 mV − + ...

Page 50

... ADM1041 Table 36. Register 1Bh, Sel CBD/SMBAlert2. Power-On Default from EEPROM Register 811Bh during Power-Up. Bit No. Name R/W 7 selcbd2 <7> R/W 6 selcbd2 <6> R/W 5 selcbd2 <5> R/W 4 selcbd2 <4> R/W 3 selcbd2 <3> R/W 2 selcbd2 <2> R/W 1 selcbd2 <1> R/W 0 selcbd2 <0> R/W Table 37. Register 1Ch, Manufacturer’ ...

Page 51

... Probe 1 cell current data (two decimal places) Probe 2 cell current data (integer) Probe 2 cell current data (two decimal places) Final test cell current data (integer) Final test cell current data (two decimal places) Probe X coordinate Probe Y coordinate Wafer number Rev Page ADM1041 ...

Page 52

... ADM1041 by reading m_pson_r. Debouncing would be done by the microprocessor. If m_pson_r changed state, the microprocessor would write the new state to m_pson_w in all ADM1041s on the SMBus fault were to occur on any output, the SMBAlert interrupt would request microprocessor attention. If this means turning all ADM1041s off, this would be done by writing a zero to the m_pson_w bit ...

Page 53

... SENSE Notes to Microprocessor (µP) support. 1. Possible ways to turn the ADM1041 on or off in response to a system request or a fault include: • Daisy chaining other ADM1041 PSON pins to the PEN pin, which is controlled by PSON on one ADM1041. • The microprocessor looks after the PSON—system interface and any shutdowns due to faults. ...

Page 54

... ADM1041 TRIM TABLE This table shows all of the trims that can be set in the ADM1041. Table 44. Description Set Load Voltage. Trim output from differential amplifier to set voltage at load. Set Load OV. Trim calibrated output from remote sense amplifier to set load OV threshold. Set False UV Clamp Threshold. Fine trim output to set voltage before OR-FET in case of load OV (at input pins) ...

Page 55

... SENSE Microprocessor support via SMBus Mode Hardware PS_ON Micorporcessor support via SMBus Mode UVB follows AC_OKLink UVB follows AC SENSE signal ovfault uvfault ocpt0 (ridethough timed out) acsnsb ocpf otp (mov5) orfetokb Share_OKb mfgl mfg2 mfg3 mfg4 m_cbd_w mfg5 Not used ADM1041 ...

Page 56

... ADM1041 Description Bit No. Trim registers, locking bit. 0 Current Sense Mode. 7 Chopper Mode. 6 Current sense dc offset adjustment (with respect to the input). 2–0 Compensates for the amplifier input offset voltage. Current sense external divider error correction 5–3 range (with respect to the input). Compensates for the ...

Page 57

... +ve ov iopin > 1. +ve uv iopin < 1. +ve uv iopin > 1. −ve ov iopin < 1. −ve ov iopin > 1. −ve uv iopin < 1. –ve uv iopin > 1. flag iopin < 1. flag iopin > 1. flag iopin < 1. flag iopin > 1. flag ov iopin = DC_OK iopin = DC_OK ADM1041 ...

Page 58

... ADM1041 Description Bit No. To set DC_OK polarity, see polDC_OK. Option: V /AC_OK/MON5. 4–2 REF To set AC_OK polarity, see polDC_OK. AC sense source. 2 PSON delay/debounce time. 1–0 DC_OK on delay. 1–0 Delay time from dc outputs being enabled to DC_OK being asserted. DC_OK off delay. 7–6 Delay time from PSON ...

Page 59

... PEN gated by acsnsok Period 100 µs 200 µs 300 µs 400 µs Threshold 100 mV 150 mV 200 mV 250 mV Threshold Threshold voltage ±5% ±100 mV ±10% ±200 mV ±15% ±300 mV ±20% ±400 mV Mode OV, UV, OC faults latch Auto-restarts after OCP or undervoltage FET option Polarity N − − ADM1041 ...

Page 60

... ADM1041 Description Bit No. Set CBD Output Polarity 5 6 Set OrFET Gate Drive 3 Polarity This is an open-drain N-FET Set DC_OK Output Polarity. 5 Also selects open-drain 5 N-channel or P-channel. Set I Clamp Release 0 SHARE threshold. Percent of nominal output voltage. Configure Soft OTP Option 0 Select CBD Latch Mode ...

Page 61

... CURRENT SENSE CALIBRATION Full Scale (No Offset), T LOADOV_TRUE Attenuation Range Current Share Trim Step (At SHRO), Current Sense Accuracy, (40 mV) V Cal. Accuracy LS_RANGE A Cal. Accuracy CLAMP V Cal. Accuracy CLMPTRIM V CLMPSTEP Rev Page ADM1041 Test Name V LSOV V LSOVSTEP V LSOVSTEP T NFOVP V LSUV V LSUVSTEP V LSUVSTEP T NFUVP V ...

Page 62

... ADM1041 Specification SHARE BUS OFFSET Current Share Offset Range Zero Current Offset Trim Step CURRENT TRANSFORMER SENSE INPUT Gain Setting 0 Gain Setting 1 CT Input Sensitivity (Gain Set 0) CT Input Sensitivity (Gain Set 1) Input Impedance Source Current Source Current Step Size Reverse Current for Extended ...

Page 63

... V IL SCL Low Time V IH SCL High Time V OL SCL, SDA Rise Time I PULLUP SCL, SDA Fall Time I LEAK Data Setup Time Data Hold Time EEPROM RELIABILITY Endurance Data Retention Rev Page ADM1041 Test Name f SCLK BUF t SU;STA t HD;STA t LOW t HIGH ...

Page 64

... Model Temperature Range ADM1041ARQ −40°C to +85°C ADM1041ARQ-REEL −40°C to +85°C ADM1041ARQ-REEL7 −40°C to +85°C 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components ...

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