EASY 6996M CPU Infineon Technologies, EASY 6996M CPU Datasheet - Page 91

• Manufacturer Part Number: EASY 6996M CPU
• Description: BOARD EVAL W/CPU ADM6996M
• Manufacturer: Infineon Technologies
• Series: Samurair

Specifications of EASY 6996M CPU

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: ADM6996M
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Primary Attributes: -
• Other names: EASY6996MCPUIN

Field
CROSS_EE
SELFX_EE
PVID3_0
PP
PPE
IPVLAN
PD
OPTE
DA
Data Sheet
Bits
15
14
13:10
9:8
7
6
5
4
3
Type
rw
rw
rw
rw
rw
rw
rw
rw
rw
Description
Crossover Auto Detect Enable
This bit is used together with the value (cross_hw) on the pin
during the power on reset and the value (wait_init) on the pin
during the normal mode to decide if PHY enables this function. This bit is
useless in Port 5.
Combine with wait_initand cross_hw, the crossover auto detect capability
is summarized as below :
{wait_init, cross_hw, cross_ee} Description
1x1
1x0
01x
000
001
Select FX
This bit is used together with the value (p4fx_hw) on the pin
the power on reset to decide if the PHY operates on the fiber mode. This
bit is useless in Port 5. Port 0, 1, 2, 3: follow selfx_ee Description and Port
4: follow {p4fx_hw, selfx_ee} Description
1x
00
01
Private VID
See 0028
Port Priority
00
01
10
11
Port Priority Enable
0
1
IP over VLAN PRI
0
1
Port Disable
0
1
Output Packet Tagging Enable
0
1
Duplex Ability
It is useless in Port 5.
0
1
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
down
Port 0, 1, 2, 3, 4: PHY works normally. Port 5: Port 5 works normally
This port will enable Crossover Auto Detect Enable function
This port will disable Crossover Auto Detect Enable function
This port will enable Crossover Auto Detect Enable function
This port will disable Crossover Auto Detect Enable function
This port will enable Crossover Auto Detect Enable function
Port 4: Port 4 will operate in the fiber mode
Port 4: Port 4 will operate in the twisted mode
Port 4: Port 4 will operate in the fiber mode
Assign packets to Queue 0
Assign packets to Queue 1
Assign packets to Queue 2
Assign packets to Queue 3
The port priority is disabled
The port priority is enabled
Use the priority bits in the tag header to assign the priority queue
Use the IP PRI to assign the priority queue
Port 0, 1, 2, 3, 4. PHY is disabled. Port 5: Port 5 is forced to link
Untagged packets are transmitted
Tagged packets are transmitted
Recommend PHY to work in the half duplex mode
Recommend PHY to work in the full duplex mode
H
~ 002C
91
H
to find the other PVID [11:4]
Revision 1.4, 2006-03-24
Registers Description
Samurai-6M/MX
ADM6996M/MX
P4FX
EESK/SDC
WAIT_INIT
during